Device power control

ABSTRACT

In various embodiments and/or usage scenarios, device power control, such as relating to one or more power control commands, requests to transition operation to a specific power mode, and/or device power management commands, is advantageous and improves one or more of: performance, reliability, unit cost, and development cost of one or more devices, such as storage devices (e.g. a Solid-State Disk (SSD)) or systems including same.

CROSS REFERENCE TO RELATED APPLICATIONS

Priority benefit claims for this application are made in theaccompanying Application Data Sheet, Request, or Transmittal (asappropriate, if any). To the extent permitted by the type of the instantapplication, this application incorporates by reference for all purposesthe following applications, all commonly owned with the instantapplication at the time the invention was made:

-   -   This application is a divisional of U.S. Ser. No. 14/854,005,        filed Sep. 14, 2015, which is a continuation of U.S. National        Stage application of PCT/IB2014/059744, filed Mar. 13, 2014,        which claims the benefit of U.S. Provisional Application Ser.        No. 61/786,110, filed Mar. 14, 2013.

BACKGROUND Field

Advancements in storage device technology and manufacturing are neededto provide improvements in cost, profitability, performance, efficiency,and utility of use.

Related Art

Unless expressly identified as being publicly or well known, mentionherein of techniques and concepts, including for context, definitions,or comparison purposes, should not be construed as an admission thatsuch techniques and concepts are previously publicly known or otherwisepart of the prior art. All references cited herein (if any), includingpatents, patent applications, and publications, are hereby incorporatedby reference in their entireties, whether specifically incorporated ornot, for all purposes.

SYNOPSIS

The invention may be implemented in numerous ways, e.g., as a process,an article of manufacture, an apparatus, a system, a composition ofmatter, and a computer readable medium such as a computer readablestorage medium (e.g., media in an optical and/or magnetic mass storagedevice such as a disk, an integrated circuit having non-volatile storagesuch as flash storage), or a computer network wherein programinstructions are sent over optical or electronic communication links.The Detailed Description provides an exposition of one or moreembodiments of the invention that enable improvements in cost,profitability, performance, efficiency, and utility of use in the fieldidentified above. The Detailed Description includes an Introduction tofacilitate understanding of the remainder of the Detailed Description.The Introduction includes Example Embodiments of one or more of systems,methods, articles of manufacture, and computer readable media inaccordance with concepts described herein. As is discussed in moredetail in the Conclusions, the invention encompasses all possiblemodifications and variations within the scope of the issued claims.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1A illustrates selected details of an embodiment of a Solid-StateDisk (SSD) including an SSD controller enabled to perform device powercontrol.

FIG. 1B illustrates selected details of various embodiments of systemsincluding one or more instances of the SSD of FIG. 1A.

FIG. 2 illustrates selected details of various embodiments of devicepower control.

FIG. 3 illustrates selected details of various embodiments of devicepower control persistence.

FIG. 4 illustrates selected details of various embodiments of devicepower control collection and distribution.

FIG. 5 illustrates selected details of various embodiments of devicepower control of an interface.

FIG. 6 illustrates selected details of various embodiments of devicepower control with respect to device power management commands.

List of Reference Symbols in Drawings Ref. Symbol Element Name 100 SSDController 101 SSD 102 Host 103 (optional) Switch/Fabric/IntermediateController 104 Intermediate Interfaces 105 OS 106 FirmWare (FW) 107Driver 107D dotted-arrow (Host Software ←→ I/O Device Communication) 108Power Control Software 109 Application 109D dotted-arrow (Application ←→I/O Device Communication via driver) 109V dotted-arrow (Application ←→I/O Device Communication via VF) 110 External Interfaces 111 HostInterfaces 112C (optional) Card Memory 113 Tag Tracking 114 Multi-DeviceManagement Software 115 Host Software 116 I/O Card 117 I/O & StorageDevices/Resources 118 Servers 119 LAN/WAN 121 Data Processing 123Engines 131 Buffer 133 DMA 135 ECC-X 137 Memory 141 Map 143 Table 151Recycler 161 ECC 171 CPU 172 CPU Core 173 Command Management 175 BufferManagement 177 Translation Management 179 Coherency Management 180Memory Interface 181 Device Management 182 Identity Management 183 PowerControl 190 Device Interfaces 191 Device Interface Logic 192 FlashDevice 193 Scheduling 194 Flash Die 196 Saved Power Mode 199 NVM 200DDevice Actions 200H Host Actions 201H Start 202H Issue (other than)Power Control Command 203D Receive Power Control Command 203H IssuePower Control Command 204D Process Power Control Command 212D Receive(other than) Power Control Command 213D Process (other than) PowerControl Command 214D Process (other than) Power Control Command 215DProcess (other than) Power Control Command 216D Process (other than)Power Control Command 299D End 301 Start 302 Install FW 302UPowerUp/Reset 303 Initialize 304 Operate 304P Power Control Command 304UPowerUp/Reset 305 Persistent? 305N No 305Y Yes 306 Change Saved 307Change Operating 312 SavedPowerMode <= ManufacturingPowerMode 313OperatingPowerMode <= SavedPowerMode 316 SavedPowerMode <= NewPowerMode317 OperatingPowerMode <= NewPowerMode 400D Device Actions 400H HostActions 401H Start 402D Receive Power Control Command (Info Collection)402H Issue Power Control Command (Info Collection) 403D ConditionallyDistribute 404D Collect Results 404H Determine Revised Power Plan 405DReceive Power Control Command (Change) 405H Issue Power Control Command(Change) 406D Conditionally Distribute 407D Perform 413D (To) OtherDevices 414D (From) Other Devices 416D (To) Other Devices 499D End 501PowerUp/Reset 502 Initialize PHY Power Mode 503 Operate PHY 503RTransition Request 504 Examine Device Power State 505 Use Provided? 505NNo 505Y Yes 506 Determine New PHY Power Mode 507 Set PHY Power Mode 600DDevice Actions 600H Host Actions 601H Start 602H Execute Software 602UUser Input (optional) 603D Receive & Process Power Control Command 603HIssue Power Control Command (Modify Map) 604D Device Power ManagementCommand Map 605D Receive & Process Device Power Management Command 605HIssue Device Power Management Command 699D End

DETAILED DESCRIPTION

A detailed description of one or more embodiments of the invention isprovided below along with accompanying figures illustrating selecteddetails of the invention. The invention is described in connection withthe embodiments. The embodiments herein are understood to be merelyexemplary, the invention is expressly not limited to or by any or all ofthe embodiments herein, and the invention encompasses numerousalternatives, modifications, and equivalents. To avoid monotony in theexposition, a variety of word labels (such as: first, last, certain,various, further, other, particular, select, some, and notable) may beapplied to separate sets of embodiments; as used herein such labels areexpressly not meant to convey quality, or any form of preference orprejudice, but merely to conveniently distinguish among the separatesets. The order of some operations of disclosed processes is alterablewithin the scope of the invention. Wherever multiple embodiments serveto describe variations in process, method, and/or program instructionfeatures, other embodiments are contemplated that in accordance with apredetermined or a dynamically determined criterion perform staticand/or dynamic selection of one of a plurality of modes of operationcorresponding respectively to a plurality of the multiple embodiments.Numerous specific details are set forth in the following description toprovide a thorough understanding of the invention. The details areprovided for the purpose of example and the invention may be practicedaccording to the claims without some or all of the details. For thepurpose of clarity, technical material that is known in the technicalfields related to the invention has not been described in detail so thatthe invention is not unnecessarily obscured.

Introduction

This introduction is included only to facilitate the more rapidunderstanding of the Detailed Description; the invention is not limitedto the concepts presented in the introduction (including explicitexamples, if any), as the paragraphs of any introduction are necessarilyan abridged view of the entire subject and are not meant to be anexhaustive or restrictive description. For example, the introductionthat follows provides overview information limited by space andorganization to only certain embodiments. There are many otherembodiments, including those to which claims will ultimately be drawn,discussed throughout the balance of the specification.

Acronyms

At least some of the various shorthand abbreviations (e.g. acronyms)defined here refer to certain elements used herein.

Acronym Description AHCI Advanced Host Controller Interface APIApplication Program Interface ATA Advanced Technology Attachment (ATAttachment) BCH Bose Chaudhuri Hocquenghem BIOS Basic Input/OutputSystem CD Compact Disk CF Compact Flash CPU Central Processing Unit CRCCyclic Redundancy Check DAS Direct Attached Storage DDR Double-Data-RateDLL Delay Locked Loop DMA Direct Memory Access DNA Direct NAND AccessDRAM Dynamic Random Access Memory DVD Digital Versatile/Video Disk DVRDigital Video Recorder ECC Error-Correcting Code eMMC EmbeddedMultiMediaCard eSATA external Serial Advanced Technology Attachment GPSGlobal Positioning System HDD Hard Disk Drive I/O Input/Output ICIntegrated Circuit IDE Integrated Drive Electronics LAN Local AreaNetwork LBA Logical Block Address LDPC Low-Density Parity-Check MLCMulti-Level Cell MMC MultiMediaCard NAS Network Attached Storage NCQNative Command Queuing NVM Non-Volatile Memory ONA Optimized NAND AccessONFI Open NAND Flash Interface OS Operating System PC Personal ComputerPCIe Peripheral Component Interconnect express (PCI express) PDAPersonal Digital Assistant PHY PHYsical interface PLL Phase Locked LoopPOS Point Of Sale RAID Redundant Array of Inexpensive/Independent DisksRASIE Redundant Array of Silicon Independent Elements ReRAM ResistiveRandom Access Memory RS Reed-Solomon SAN Storage Attached Network SASSerial Attached Small Computer System Interface (Serial Attached SCSI)SATA Serial Advanced Technology Attachment (Serial ATA) SCSI SmallComputer System Interface SD Secure Digital SDR Single-Data-Rate SLCSingle-Level Cell SMART Self-Monitoring Analysis and ReportingTechnology SSD Solid-State Disk/Drive SSP Serial Small Computer SystemInterface Protocol (Serial SCSI Protocol) UFS Unified Flash Storage USBUniversal Serial Bus VF Virtual Function WAN Wide Area Network

In various embodiments and/or usage scenarios, device power control,such as via one or more power control commands, is advantageous andimproves one or more of: performance, reliability, unit cost, anddevelopment cost of one or more devices, such as storage devices (e.g.an SSD) or systems including same. In a first aspect, a queued powercontrol command is issued from a source agent (e.g. a host such as acomputer) to a sink agent (e.g. a storage device such as an SSD). Thequeued characteristic of the queued power control command enablesprocessing without completing and/or aborting commands previously issuedto the sink agent and not yet completed or aborted. For example, thequeued power control command is processed immediately upon receipt,and/or independently of previously received but not yet completed oraborted commands.

In a second aspect, an optionally persistent power control command isissued from a host to a device. If persistent, then effects of theoptionally persistent power control command remain in effect until anext power control command (e.g. across one or more power up and/orreset events). If not persistent, then effects of the optionallypersistent power control command cease upon a next power up event, anext reset event, and/or a next power control command. In someembodiments and/or usage scenarios, a persistent power control commandenables subsequent device boots (e.g. in response to a power up and/orreset event) according to a revised power budget, such as not exceedinga new power dissipation maximum.

In a third aspect, a host issues to a device a power control command toobtain power information from the device, and selectively any devicescoupled to the device. The device distributes thepower-information-obtaining power control command to the coupled devices(if any), and collects resulting information from the coupled devicesand itself. The device returns the collected information to the host.The host, based at least in part on the returned collected information,determines a new power operating point and selectively issues a powercontrol command to change power to the device (as well as the coupleddevices, if any). The device then distributes the power-changing powercontrol command to the coupled devices as appropriate and processes thecommand itself.

In a fourth aspect, an interface (e.g. a PHY interface of a device or ahost) is selectively and/or conditionally operable in a compatible modeand an enhanced mode. While operating in the compatible mode, theinterface is fully compliant with at least one storage interfacestandard. While operating in the enhanced mode, the interface iscompliant with the at least one storage interface standard except withregards to processing requests to transition to a specific power mode.The requests are processed conditionally and/or selectively dependent ona power state of the device, and a request to transition to a particularpower mode conditionally and/or selectively results in operation in theparticular mode or another power mode that is different than theparticular power mode.

In a fifth aspect, a device is enabled to consult a device powermanagement command map to determine which of a plurality of operatingpower states to operate in accordance with in response to reception of adevice power management command. A host runs software (optionally withuser input) to send a power control command that specifies one or moremodifications to the device power management command map. Subsequentlyreceived device power management commands are interpreted in accordancewith the modifications. Thus mapping between device power managementcommands and operating power states of the device is selectively and/ordynamically maintained.

An example of a command is a directive to perform one or moreoperations. A source agent provides a command to one or more sinkagents. Exemplary source/sink agents include initiator/target,master/slave, and host/device. E.g. a host computer operating as aSCSI/iSCSI/SATA/SAS initiator is a command source agent that providescommands to a storage device operating as a SCSI/iSCSI/SATA/SAS targetthat receives the commands and in response performs operations inaccordance with the commands. Exemplary commands include read. write,power control, and device power management commands. A commandoptionally includes one or more parameters, e.g. an LBA, a persistenceand/or timeline indicator, a maximum power level, an average powerlevel, a power change fraction, percentage, or amount, a device powermanagement to device operating power state mapping, and any combinationof any one or more of the foregoing.

Examples of a source agent include a computer (e.g. a workstationcomputer, a server computer, a PC, a laptop computer, a notebookcomputer, a netbook computer, a tablet device or computer, an ultrabookcomputer, and an automotive media computer). Further examples of asource agent include a server (e.g. a storage server) and a storagesub-system (e.g. a SAN, a NAS device, a DAS device, and a storageappliance). Further examples of a source agent include a consumerelectronics element (e.g. an electronic reading device (such as ane-reader), a FDA, a navigation system, a GPS device (such as a handheldGPS device), a media player, a television, a media recorder, a DVR, adigital camera, a cellular handset, a cordless telephone handset, and anelectronic game.). Further examples of a source agent include variousautomotive electronic systems (e.g. an automotive control system such asan automotive media control system). Further examples of a source agentinclude various business electronic systems (e.g. a printer, copier orfax machine or all-in-one device, a POS device and/or terminal, and acash-register).

Examples of a sink agent include various I/O agents and/or devices, suchas storage devices (e.g. an optical storage device, a magnetic storagedevice, a mechanical storage device, and a solid-state storage device)and storage electronics (e.g. a disk drive, a magnetic disk drive, asolid-state disk drive, a solid-state disk drive having one or moreflash memories, and a tape drive). Further examples of a sink agentinclude various devices compatible with various interface standards,such as various storage devices compatible with various storageinterface standards (e.g. a USB interface standard, a CF interfacestandard, an MMC interface standard, an eMMC interface standard, aThunderbolt interface standard, a UFS interface standard, an SDinterface standard, a Memory Stick interface standard, an xD-picturecard interface standard, an IDE interface standard, a SATA interfacestandard, an eSATA interface standard, a SCSI interface standard, a SASinterface standard, a Fibre Channel interface standard, an Ethernetinterface standard, and a PCIe interface standard).

An example of sending a command (e.g. from a sink agent to a sourceagent) is communication (directly or indirectly) via any one or moreinterfaces, such as interfaces compatible with the aforementionedstorage interface standards. Commands are communicated variously via anycombination of programmed I/O, memory accesses, DMA, and so forth, e.g.,via direct communication of commands, pointers to work lists of commandsin memory, or any combination thereof.

Commands are optionally queued or optionally not queued, individuallyand/or according to specific command, command parameter, and/oroperating context. An example of a queued command is a read command thatis performed in no particular order with respect to other queued (e.g.read) commands. An exemplary queuing operating context is SATA NCQ.Another example of a queued command is a power control command that isexplicitly marked as queued and/or understood by source and sink agentsto be interpreted as a queued command. In some embodiments and/or usagescenarios, queued commands are performed by sink agents in anyconvenient order. For example, in a particular SATA NCQ operatingenvironment, a SATA device performs read and write commands in an orderdetermined by location of physical media sectors relating to thecommands and performs power control commands as immediately aspractical.

In some embodiments and/or usage scenarios, a queued command is placedon a queue with other previously received but as yet unprocessed queuedcommands, and then acted on by an order determined by the sink agent. Anexemplary order is determined, e.g., to improve performance, such asbandwidth, latency, and/or power consumption.

In some embodiments and/or usage scenarios, queued power controlcommands are performed at a time that is independent of timing of otherqueued commands, such as queued commands that are queued and/orpreviously begun at a time that a power control command is beginningprocessing, undergoing processing, or completing processing. Thus insome embodiments and/or usage scenarios, a queued power control commandis processed before a queued command that is not a power controlcommand, even when the queued power control command is sent or receivedafter the queued command that is not a power control command.

Various example embodiments of power control commands includevendor-specific commands, non-standard commands, and standard commandsaugmented with one or more non-standard parameters.

Examples of parallel storage interfaces are ATA, such as used by an IDEstorage device (e.g. drive), and (parallel) SCSI. Examples of serialstorage interfaces are SATA and SAS. Some serial storage interfacesimplement commands that are compatible with comparable parallel storageinterface commands, e.g. some SATA commands are compatible with some ATAcommands, and some SAS commands are compatible with some SCSI commands.

In some embodiments having one or more sink agents that implementstorage via non-volatile memory, example interfaces to the non-volatilememory (e.g. flash memory) include interfaces that are compatible withone or more of an ONFI interface, a Toggle-mode interface, a DDRsynchronous interface, a DDR2 synchronous interface, a synchronousinterface, and an asynchronous interface.

Example Embodiments

In concluding the introduction to the detailed description, what followsis a collection of example embodiments, including at least someexplicitly enumerated as “ECs” (Example Combinations), providingadditional description of a variety of embodiment types in accordancewith the concepts described herein; these examples are not meant to bemutually exclusive, exhaustive, or restrictive; and the invention is notlimited to these example embodiments but rather encompasses all possiblemodifications and variations within the scope of the issued claims andtheir equivalents.

EC1) A method comprising:

-   -   receiving a first command and then a second command;    -   processing the second command in response to the receiving;    -   wherein the receiving and the processing are in a storage        device;    -   wherein the second command comprises power control information;        and    -   wherein the processing commences while the first command is        outstanding.

EC2) The method of EC1, wherein the receiving is via an interface of thestorage device that is compatible with at least one storage interfacestandard.

EC3) The method of EC1, further comprising processing the first commandin accordance with the power control information.

EC4) The method of EC1, further comprising the storage devicepowering-up in accordance with at least a portion of the power controlinformation.

EC5) The method of EC4, wherein the portion of the power controlinformation is different than corresponding power control informationthat is in accordance with manufacturing of the storage device.

EC6) The method of EC1, further comprising the storage device resettingin accordance with at least a portion of the power control information.

EC7) The method of EC1, further comprising operating the storage devicein accordance with at least a portion of the power control informationacross a reset and/or a power cycle of the storage device.

EC8) The method of EC1, further comprising the storage device passingalong at least a portion of the power control information to at leastone other storage device.

EC9) The method of EC8, further comprising the storage device receivingpower usage information from the at least one other storage device.

EC10) The method of EC9, wherein a host provides the first and thesecond commands, and further comprising the storage device passing alongat least a portion of the power usage information to the host.

EC11) The method of EC1, wherein the storage device comprisesnon-volatile memory, and the processing comprises altering what portionof the non-volatile memory is maximally enabled to be concurrentlyactive.

EC12) The method of EC11, wherein the non-volatile memory comprises oneor more flash memory devices, and the altering comprises altering howmany of the flash memory devices are maximally enabled to beconcurrently active.

EC13) The method of EC12, wherein the altering how many of the flashmemory devices are maximally enabled to be concurrently active comprisesaccessing predetermined flash memory device power consumptioninformation based at least in part on at least a portion of the powercontrol information.

EC 14) The method of EC12, further comprising measuring powerconsumption of at least some of the flash memory devices, and whereinthe altering how many of the flash memory devices are maximally enabledto be concurrently active comprises accessing at least a portion of themeasured power consumption based at least in part on at least a portionof the power control information.

EC15) The method of EC1, wherein the storage device comprises one ormore interfaces to non-volatile memory, and the processing comprisesaltering what portion of the interfaces are maximally enabled to beconcurrently active.

EC16) The method of EC1, wherein the storage device comprises areference frequency generator, and the processing comprises altering afrequency that the reference frequency generator generates.

EC17) The method of EC1, wherein the processing comprises modifyingmapping information that enables mapping device power managementcommands to corresponding operating power states of the storage device,the modifying being based at least in part on information provided bythe second command, and further comprising:

-   -   in the storage device, receiving an instance of a particular one        of the device power management commands, and in response        accessing the mapping information to determine a particular one        of the operating power states, the accessing being based at        least in part on the instance; and    -   in the storage device, in response to the accessing, operating        the storage device in accordance with the particular operating        power state.

EC18) A system comprising:

-   -   means for receiving a first command and then a second command;    -   means for processing the second command in response to the means        for receiving;    -   wherein a storage device comprises the means for receiving and        the means for processing;    -   wherein the second command comprises power control information;        and    -   wherein the means for processing commences processing the second        command while the first command is outstanding.

EC19) The system of EC18, wherein the means for receiving comprises aninterface of the storage device that is compatible with at least onestorage interface standard.

EC20) The system of EC 18, further comprising means for processing thefirst command in accordance with the power control information.

EC21) The system of EC18, wherein the storage device is enabled topower-up in accordance with at least a portion of the power controlinformation.

EC22) The system of EC21, wherein the portion of the power controlinformation is different than corresponding power control informationthat is in accordance with manufacturing of the storage device.

EC23) The system of EC18, further comprising means for the storagedevice to reset in accordance with at least a portion of the powercontrol information.

EC24) The system of EC18, further comprising means for operating thestorage device in accordance with at least a portion of the powercontrol information across a reset and/or a power cycle of the storagedevice.

EC25) The system of EC18, further comprising means for the storagedevice to pass along at least a portion of the power control informationto at least one other storage device.

EC26) The system of EC25, further comprising means for the storagedevice to receive power usage information from the at least one otherstorage device.

EC27) The system of EC26, wherein a host provides the first and thesecond commands, and further comprising means for the storage device topass along at least a portion of the power usage information to thehost.

EC28) The system of EC18, wherein the storage device comprisesnon-volatile memory, and the means for processing comprises means foraltering what portion of the non-volatile memory is maximally enabled tobe concurrently active.

EC29) The system of EC28, wherein the non-volatile memory comprises oneor more flash memory devices, and the means for altering comprises meansfor altering how many of the flash memory devices are maximally enabledto be concurrently active.

EC30) The system of EC29, wherein the means for altering how many of theflash memory devices are maximally enabled to be concurrently activecomprises means for accessing predetermined flash memory device powerconsumption information based at least in part on at least a portion ofthe power control information.

EC31) The system of EC29, further comprising means for measuring powerconsumption of at least some of the flash memory devices, and whereinthe means for altering how many of the flash memory devices aremaximally enabled to be concurrently active comprises means foraccessing at least a portion of the measured power consumption based atleast in part on at least a portion of the power control information.

EC32) The system of EC18, wherein the storage device comprises one ormore interfaces to non-volatile memory, and the means for processingcomprises means for altering what portion of the interfaces aremaximally enabled to be concurrently active.

EC33) The system of EC18, wherein the storage device comprises areference frequency generator, and the means for processing comprisesmeans for altering a frequency that the reference frequency generatorgenerates.

EC34) The system of EC18, wherein the means for processing comprisesmeans for modifying mapping information that enables mapping devicepower management commands to corresponding operating power states of thestorage device, the modifying being based at least in part oninformation provided by the second command, and further comprising:

-   -   means for receiving, in the storage device, an instance of a        particular one of the device power management commands, and in        response accessing the mapping information to determine a        particular one of the operating power states, the accessing        being based at least in part on the instance; and    -   means for, in response to the accessing, operating the storage        device in accordance with the particular operating power state.

EC35) A non-transitory tangible computer readable medium having a set ofinstructions stored therein that when executed by a processing elementcause the processing clement to perform and/or control operationscomprising:

-   -   receiving a first command and then a second command;    -   processing the second command in response to the receiving;    -   wherein the receiving and the processing are in a storage        device;    -   wherein the second command comprises power control information;        and    -   wherein the processing commences while the first command is        outstanding.

EC36) The non-transitory tangible computer readable medium of EC35,wherein the receiving is via an interface of the storage device that iscompatible with at least one storage interface standard.

EC37) The non-transitory tangible computer readable medium of EC35,wherein the operations further comprise processing the first command inaccordance with the power control information.

EC38) The non-transitory tangible computer readable medium of EC35,wherein the operations further comprise the storage device powering-upin accordance with at least a portion of the power control information.

EC39) The non-transitory tangible computer readable medium of EC38,wherein the portion of the power control information is different thancorresponding power control information that is in accordance withmanufacturing of the storage device.

EC40) The non-transitory tangible computer readable medium of EC35,wherein the operations further comprise the storage device resetting inaccordance with at least a portion of the power control information.

EC41) The non-transitory tangible computer readable medium of EC35,wherein the operations further comprise operating the storage device inaccordance with at least a portion of the power control informationacross a reset and/or a power cycle of the storage device.

EC42) The non-transitory tangible computer readable medium of EC35,wherein the operations further comprise the storage device passing alongat least a portion of the power control information to at least oneother storage device.

EC43) The non-transitory tangible computer readable medium of EC42,wherein the operations further comprise the storage device receivingpower usage information from the at least one other storage device.

EC44) The non-transitory tangible computer readable medium of EC43,wherein a host provides the first and the second commands, and theoperations further comprise the storage device passing along at least aportion of the power usage information to the host.

EC45) The non-transitory tangible computer readable medium of EC35,wherein the storage device comprises non-volatile memory, and theprocessing comprises altering what portion of the non-volatile memory ismaximally enabled to be concurrently active.

EC46) The non-transitory tangible computer readable medium of EC45,wherein the non-volatile memory comprises one or more flash memorydevices, and the altering comprises altering how many of the flashmemory devices are maximally enabled to be concurrently active.

EC47) The non-transitory tangible computer readable medium of EC46,wherein the altering how many of the flash memory devices are maximallyenabled to be concurrently active comprises accessing predeterminedflash memory device power consumption information based at least in parton at least a portion of the power control information.

EC48) The non-transitory tangible computer readable medium of EC46,wherein the operations further comprise measuring power consumption ofat least some of the flash memory devices, and the altering how many ofthe flash memory devices are maximally enabled to be concurrently activecomprises accessing at least a portion of the measured power consumptionbased at least in part on at least a portion of the power controlinformation.

EC49) The non-transitory tangible computer readable medium of EC35,wherein the storage device comprises one or more interfaces tonon-volatile memory, and the processing comprises altering what portionof the interfaces are maximally enabled to he concurrently active.

EC50) The non-transitory tangible computer readable medium of EC35,wherein the storage device comprises a reference frequency generator,and the processing comprises altering a frequency that the referencefrequency generator generates.

EC51) The non-transitory tangible computer readable medium of EC35,wherein the processing comprises modifying mapping information thatenables mapping device power management commands to correspondingoperating power states of the storage device, the modifying being basedat least in part on information provided by the second command, andwherein the operations further comprise:

-   -   receiving an instance of a particular one of the device power        management commands, and in response accessing the mapping        information to determine a particular one of the operating power        states, the accessing being based at least in part on the        instance; and    -   in response to the accessing, operating the storage device in        accordance with the particular operating power state.

EC52) A storage device comprising:

-   -   logic circuitry enabled to receive a first command and then a        second command;    -   logic circuitry enabled to process the second command in        response to the logic circuitry enabled to receive;    -   wherein the second command comprises power control information;        and    -   wherein the logic circuitry enabled to process commences        processing the second command while the first command is        outstanding.

EC53) The storage device of EC52, wherein the logic circuitry enabled toreceive comprises an interface of the storage device that is compatiblewith at least one storage interface standard.

EC54) The storage device of EC52, further comprising logic circuitryenabled to process the first command in accordance with the powercontrol information.

EC55) The storage device of EC52, further comprising logic circuitryenabled to power-up the storage device in accordance with at least aportion of the power control information.

EC56) The storage device of EC55, wherein the portion of the powercontrol information is different than corresponding power controlinformation that is in accordance with manufacturing of the storagedevice.

EC57) The storage device of EC52, further comprising logic circuitryenabled to reset the storage device in accordance with at least aportion of the power control information.

EC58) The storage device of EC52, further comprising logic circuitryenabled to operate the storage device in accordance with at least aportion of the power control information across a reset and/or a powercycle of the storage device.

EC59) The storage device of EC52, further comprising logic circuitryenabled to pass along at least a portion of the power controlinformation to at least one other storage device.

EC60) The storage device of EC59, further comprising logic circuitryenabled to receive power usage information from the at least one otherstorage device.

EC61) The storage device of EC60, wherein a host provides the first andthe second commands, and further comprising logic circuitry enabled topass along at least a portion of the power usage information to thehost.

EC62) The storage device of EC52, further comprising non-volatilememory, and wherein the processing comprises altering what portion ofthe non-volatile memory is maximally enabled to be concurrently active.

EC63) The storage device of EC62, wherein the non-volatile memorycomprises one or more flash memory devices, and the altering comprisesaltering how many of the flash memory devices are maximally enabled tobe concurrently active.

EC64) The storage device of EC63, wherein the altering how many of theflash memory devices are maximally enabled to be concurrently activecomprises accessing predetermined flash memory device power consumptioninformation based at least in part on at least a portion of the powercontrol information.

EC65) The storage device of EC63, further comprising logic circuitryenabled to measure power consumption of at least some of the flashmemory devices, and wherein the altering how many of the flash memorydevices are maximally enabled to be concurrently active comprisesaccessing at least a portion of the measured power consumption based atleast in part on at least a portion of the power control information.

EC66) The storage device of EC52, further comprising one or moreinterfaces to non-volatile memory. and wherein the processing comprisesaltering what portion of the interfaces are maximally enabled to beconcurrently active.

EC67) The storage device of EC52, further comprising a referencefrequency generator, and wherein the processing comprises altering afrequency that the reference frequency generator generates.

EC68) The storage device of EC52, wherein the processing comprisesmodifying mapping information that enables mapping device powermanagement commands to corresponding operating power states of thestorage device, the modifying being based at least in part oninformation provided by the second command, and further comprising:

-   -   logic circuitry enabled to receive an instance of a particular        one of the device power management commands, and in response to        access the mapping information to determine a particular one of        the operating power states, the access being based at least in        part on the instance; and    -   logic circuitry enabled, in response to the accessing, to        operate the storage device in accordance with the particular        operating power state.

EC69) A method comprising:

-   -   in a storage device, receiving a command in accordance with a        storage interface standard, the command comprising power control        information;    -   operating the storage device in accordance with at least a        persistent portion of the power control information across a        reset of the storage device;    -   operating the storage device in accordance with the persistent        portion across a power cycle of the storage device; and    -   wherein the reset and the power cycle occur after the receiving.

EC70) The method of EC69, wherein the operating the storage device inaccordance with the at least the persistent portion enables notexceeding a new power dissipation maximum.

EC71) The method of EC69, wherein the command is a second command, andfurther comprising:

-   -   in the storage device, receiving, before the receiving of the        second command, a first command in accordance with the storage        interface standard; and    -   commencing processing of the second command while the first        command is outstanding.

EC72) The method of EC71, wherein the storage device comprisesnon-volatile memory, and the processing comprises altering what portionof the non-volatile memory is maximally enabled to be concurrentlyactive.

EC73) The method of EC72, wherein the non-volatile memory comprises oneor more flash memory devices, and the altering comprises altering howmany of the flash memory devices are maximally enabled to beconcurrently active.

EC74) The method of EC71, wherein the storage device comprises one ormore interfaces to non-volatile memory, and the processing comprisesaltering what portion of the interfaces are maximally enabled to beconcurrently active.

EC75) A system comprising:

-   -   means for receiving, in a storage device, a command in        accordance with a storage interface standard, the command        comprising power control information;    -   means for operating the storage device in accordance with at        least a persistent portion of the power control information        across a reset of the storage device;    -   means for operating the storage device in accordance with the at        least the persistent portion across a power cycle of the storage        device; and    -   wherein the reset and the power cycle occur after receiving the        command.

EC76) The system of EC75, wherein the means for operating the storagedevice in accordance with the at least the persistent portion enablesnot exceeding a new power dissipation maximum.

EC77) The system of EC75, wherein the command is a second command, andfurther comprising:

-   -   means for receiving, in the storage device and before the        receiving of the second command, a first command in accordance        with the storage interface standard; and    -   means for commencing processing of the second command while the        first command is outstanding.

EC78) The system of EC77, wherein the storage device comprisesnon-volatile memory, and the processing comprises altering what portionof the non-volatile memory is maximally enabled to be concurrentlyactive.

EC79) The system of EC78, wherein the non-volatile memory comprises oneor more flash memory devices, and the altering comprises altering howmany of the flash memory devices are maximally enabled to beconcurrently active.

EC80) The system of EC77, wherein the storage device comprises one ormore interfaces to non-volatile memory, and the processing comprisesaltering what portion of the interfaces are maximally enabled to beconcurrently active.

EC81) A non-transitory tangible computer readable medium having a set ofinstructions stored therein that when executed by a processing elementcause the processing element to perform and/or control operationscomprising:

-   -   in a storage device, receiving a command in accordance with a        storage interface standard, the command comprising power control        information;    -   operating the storage device in accordance with at least a        persistent portion of the power control information across a        reset of the storage device;    -   operating the storage device in accordance with the at least the        persistent portion across a power cycle of the storage device;        and    -   wherein the reset and the power cycle occur after the receiving.

EC82) The non-transitory tangible computer readable medium of EC81,wherein the operating the storage device in accordance with the at leastthe persistent portion enables not exceeding a new power dissipationmaximum.

EC83) The non-transitory tangible computer readable medium of EC81,wherein the command is a second command, and the operations furthercomprise:

-   -   in the storage device, receiving, before the receiving of the        second command, a first command in accordance with the storage        interface standard; and    -   commencing processing of the second command while the first        command is outstanding.

EC84) The non-transitory tangible computer readable medium of EC83,wherein the storage device comprises non-volatile memory, and theprocessing comprises altering what portion of the non-volatile memory ismaximally enabled to be concurrently active.

EC85) The non-transitory tangible computer readable medium of EC84,wherein the non-volatile memory comprises one or more flash memorydevices, and the altering comprises altering how many of the flashmemory devices are maximally enabled to be concurrently active.

EC86) The non-transitory tangible computer readable medium of EC83,wherein the storage device comprises one or more interfaces tonon-volatile memory, and the processing comprises altering what portionof the interfaces are maximally enabled to be concurrently active.

EC87) A storage device comprising:

-   -   logic circuitry enabled to receive a command in accordance with        a storage interface standard, the command comprising power        control information;    -   logic circuitry enabled to operate the storage device in        accordance with at least a persistent portion of the power        control information across a reset of the storage device;    -   logic circuitry enabled to operate the storage device in        accordance with the at least the persistent portion across a        power cycle of the storage device; and    -   wherein the reset and the power cycle occur after the receiving.

EC88) The storage device of EC87, wherein the operating the storagedevice in accordance with the at least the persistent portion enablesnot exceeding a new power dissipation maximum.

EC89) The storage device of EC87, wherein the command is a secondcommand, and further comprising:

-   -   logic circuitry enabled to receive, before the receiving of the        second command, a first command in accordance with the storage        interface standard; and    -   logic circuitry enabled to commence processing of the second        command while the first command is outstanding.

EC90) The storage device of EC89, wherein the storage device comprisesnon-volatile memory, and the processing comprises altering what portionof the non-volatile memory is maximally enabled to be concurrentlyactive.

EC91) The storage device of EC90, wherein the non-volatile memorycomprises one or more flash memory devices, and the altering comprisesaltering how many of the flash memory devices are maximally enabled tobe concurrently active.

EC92) The storage device of EC89, wherein the storage device comprisesone or more interfaces to non-volatile memory, and the processingcomprises altering what portion of the interfaces are maximally enabledto be concurrently active.

EC93) A method comprising:

-   -   in a storage device, receiving a command in accordance with a        storage interface standard, the command comprising power control        information;    -   via the storage device, passing along at least a portion of the        power control information to at least one other storage device;        and    -   in the storage device, receiving power usage information from        the at least one other storage device.

EC94) The method of EC93, wherein a host provides the command, andfurther comprising the storage device passing along at least a portionof the power usage information to the host.

EC95) The method of EC93, wherein the command is a second command, andfurther comprising:

-   -   in the storage device, receiving, before the receiving of the        second command, a first command in accordance with the storage        interface standard; and    -   commencing processing of the second command while the first        command is outstanding.

EC96) The method of EC95, wherein the storage device comprisesnon-volatile memory, and the processing comprises altering what portionof the non-volatile memory is maximally enabled to be concurrentlyactive.

EC97) The method of EC96, wherein the non-volatile memory comprises oneor more flash memory devices, and the altering comprises altering howmany of the flash memory devices are maximally enabled to beconcurrently active.

EC98) The method of EC95, wherein the storage device comprises one ormore interfaces to non-volatile memory, and the processing comprisesaltering what portion of the interfaces are maximally enabled to beconcurrently active.

EC99) A system comprising:

-   -   means for receiving, in a storage device, a command in        accordance with a storage interface standard, the command        comprising power control information;    -   means for passing along, via the storage device, at least a        portion of the power control information to at least one other        storage device; and    -   means for receiving power usage information, in the storage        device, from the at least one other storage device.

EC100) The system of EC99, wherein a host provides the command, andfurther comprising means for passing along at least a portion of thepower usage information to the host.

EC 101) The system of EC99, wherein the command is a second command, andfurther comprising:

-   -   means for receiving, in the storage device and before the        receiving of the second command, a first command in accordance        with the storage interface standard; and    -   means for commencing processing of the second command while the        first command is outstanding.

EC102) The system of EC101, wherein the storage device comprisesnon-volatile memory, and the processing comprises altering what portionof the non-volatile memory is maximally enabled to be concurrentlyactive.

EC103) The system of EC102, wherein the non-volatile memory comprisesone or more flash memory devices, and the altering comprises alteringhow many of the flash memory devices are maximally enabled to beconcurrently active.

EC104) The system of EC101, wherein the storage device comprises one ormore interfaces to non-volatile memory, and the processing comprisesaltering what portion of the interfaces are maximally enabled to beconcurrently active.

EC105) A non-transitory tangible computer readable medium having a setof instructions stored therein that when executed by a processingclement cause the processing element to perform and/or controloperations comprising:

-   -   in a storage device, receiving a command in accordance with a        storage interface standard, the command comprising power control        information;    -   via the storage device, passing along at least a portion of the        power control information to at least one other storage device;        and    -   in the storage device, receiving power usage information from        the at least one other storage device.

EC106) The non-transitory tangible computer readable medium of EC105,wherein a host provides the command, and wherein the operations furthercomprise the storage device passing along at least a portion of thepower usage information to the host.

EC107) The non-transitory tangible computer readable medium of EC105,wherein the command is a second command, and wherein the operationsfurther comprise:

-   -   in the storage device, receiving, before the receiving of the        second command, a first command in accordance with the storage        interface standard; and    -   commencing processing of the second command while the first        command is outstanding.

EC108) The non-transitory tangible computer readable medium of EC107,wherein the storage device comprises non-volatile memory, and theprocessing comprises altering what portion of the non-volatile memory ismaximally enabled to be concurrently active.

EC109) The non-transitory tangible computer readable medium of EC 108,wherein the non-volatile memory comprises one or more flash memorydevices, and the altering comprises altering how many of the flashmemory devices are maximally enabled to be concurrently active.

EC110) The non-transitory tangible computer readable medium of EC107,wherein the storage device comprises one or more interfaces tonon-volatile memory, and the processing comprises altering what portionof the interfaces are maximally enabled to be concurrently active.

EC111) A storage device comprising:

-   -   logic circuitry enabled to receive a command in accordance with        a storage interface standard, the command comprising power        control information;    -   logic circuitry enabled to pass along at least a portion of the        power control information to at least one other storage device;        and    -   logic circuitry enabled to receive power usage information from        the at least one other storage device.

EC112) The storage device of EC111, wherein a host provides the command,and the storage device is enabled to pass along at least a portion ofthe power usage information to the host.

EC113) The storage device of EC111, wherein the command is a secondcommand, and further comprising:

-   -   logic circuitry enabled to receive, before the receiving of the        second command, a first command in accordance with the storage        interface standard; and    -   logic circuitry enabled to commence processing of the second        command while the first command is outstanding.

EC114) The storage device of EC113, further comprising non-volatilememory, and wherein the processing comprises altering what portion ofthe non-volatile memory is maximally enabled to be concurrently active.

EC115) The storage device of EC114, wherein the non-volatile memorycomprises one or more flash memory devices, and the altering comprisesaltering how many of the flash memory devices are maximally enabled tobe concurrently active.

EC116) The storage device of EC113, further comprising one or moreinterfaces to non-volatile memory, and wherein the processing comprisesaltering what portion of the interfaces are maximally enabled to beconcurrently active.

EC117) A method comprising:

-   -   while operating an interface in accordance with a current power        mode and in a context of a current operating power state,        receiving a request to transition the operating of the interface        to a specified power mode;    -   in response to the receiving, accessing information concerning        the current operating power state;    -   based at least in part on at least some results of the        accessing, determining a new power mode;    -   operating the interface in accordance with the new power mode;        and    -   wherein the new power mode is different than the specified power        mode.

EC118) The method of EC117, wherein the operating the interface inaccordance with the new power mode is conditional, and furthercomprising conditionally operating the interface in accordance with thespecified power mode.

EC119) The method of EC117, wherein the interface is compatible with atleast one storage interface standard.

EC120) The method of EC117, wherein the interface is comprised in astorage device that comprises the information concerning the currentoperating power state.

EC121) The method of EC 117, wherein the interface is comprised in ahost that comprises the information concerning the current operatingpower state.

EC122) The method of EC117, wherein the specified power mode is ahigher-power mode than the current power mode, and the new power mode isidentical to the current power mode.

EC123) The method of EC122, wherein the current operating power stateprioritizes decreased power over increased performance.

EC124) The method of EC117, wherein the specified power mode is alower-power mode than the current power mode, and the new power mode isidentical to the current power mode.

EC125) The method of EC124, wherein the current operating power stateprioritizes increased performance over decreased power.

EC126) A system comprising:

-   -   means for, while operating an interface in accordance with a        current power mode and in a context of a current operating power        state, receiving a request to transition the operating of the        interface to a specified power mode;    -   means for, in response to the receiving, accessing information        concerning the current operating power state;    -   means for, based at least in part on at least some results of        the means for accessing, determining a new power mode;    -   means for operating the interface in accordance with the new        power mode; and    -   wherein the new power mode is different than the specified power        mode.

EC127) The system of EC126, wherein the operating the interface inaccordance with the new power mode is conditional, and furthercomprising means for conditionally operating the interface in accordancewith the specified power mode.

EC128) The system of EC126, wherein the interface is compatible with atleast one storage interface standard.

EC129) The system of EC126, wherein the interface is comprised in astorage device that comprises the information concerning the currentoperating power state.

EC130) The system of EC126, wherein the interface is comprised in a hostthat comprises the information concerning the current operating powerstate.

EC131) The system of EC126, wherein the specified power mode is ahigher-power mode than the current power mode, and the new power mode isidentical to the current power mode.

EC132) The system of EC131, wherein the current operating power stateprioritizes decreased power over increased performance.

EC133) The system of EC126, wherein the specified power mode is alower-power mode than the current power mode, and the new power mode isidentical to the current power mode.

EC134) The system of EC133, wherein the current operating power stateprioritizes increased performance over decreased power.

EC135) A non-transitory tangible computer readable medium having a setof instructions stored therein that when executed by a processingclement cause the processing element to perform and/or controloperations comprising:

-   -   while operating an interface in accordance with a current power        mode and in a context of a current operating power state,        receiving a request to transition the operating of the interface        to a specified power mode;    -   in response to the receiving, accessing information concerning        the current operating power state;    -   based at least in part on at least some results of the        accessing, determining a new power mode;    -   operating the interface in accordance with the new power mode;        and    -   wherein the new power mode is different than the specified power        mode.

EC136) The non-transitory tangible computer readable medium of EC135,wherein the operating the interface in accordance with the new powermode is conditional, and wherein the operations further compriseconditionally operating the interface in accordance with the specifiedpower mode.

EC137) The non-transitory tangible computer readable medium of EC135,wherein the interface is compatible with at least one storage interfacestandard.

EC138) The non-transitory tangible computer readable medium of EC135,wherein the interface is comprised in a storage device that comprisesthe information concerning the current operating power state.

EC139) The non-transitory tangible computer readable medium of EC135,wherein the interface is comprised in a host that comprises theinformation concerning the current operating power state.

EC140) The non-transitory tangible computer readable medium of EC135,wherein the specified power mode is a higher-power mode than the currentpower mode, and the new power mode is identical to the current powermode.

EC141) The non-transitory tangible computer readable medium of EC140,wherein the current operating power state prioritizes decreased powerover increased performance.

EC142) The non-transitory tangible computer readable medium of EC135,wherein the specified power mode is a lower-power mode than the currentpower mode, and the new power mode is identical to the current powermode.

EC143) The non-transitory tangible computer readable medium of EC142,wherein the current operating power state prioritizes increasedperformance over decreased power.

EC144) An apparatus comprising:

-   -   logic circuitry enabled, while operating an interface in        accordance with a current power mode and in a context of a        current operating power state, to receive a request to        transition the operating of the interface to a specified power        mode;    -   logic circuitry enabled, in response to the receiving, to access        information concerning the current operating power state;    -   logic circuitry enabled, based at least in part on at least some        results of the accessing, to determine a new power mode;    -   logic circuitry enabled to operate the interface in accordance        with the new power mode; and    -   wherein the new power mode is different than the specified power        mode.

EC145) The apparatus of EC144, wherein the operating the interface inaccordance with the new power mode is conditional, and furthercomprising logic circuitry enabled to conditionally operate theinterface in accordance with the specified power mode.

EC146) The apparatus of EC144, wherein the interface is compatible withat least one storage interface standard.

EC147) The apparatus of EC144, wherein the interface is comprised in astorage device that comprises the information concerning the currentoperating power state.

EC148) The apparatus of EC144, wherein the interface is comprised in ahost that comprises the information concerning the current operatingpower state.

EC149) The apparatus of EC144, wherein the specified power mode is ahigher-power mode than the current power mode, and the new power mode isidentical to the current power mode.

EC150) The apparatus of EC149, wherein the current operating power stateprioritizes decreased power over increased performance.

EC151) The apparatus of EC144, wherein the specified power mode is alower-power mode than the current power mode, and the new power mode isidentical to the current power mode.

EC152) The apparatus of EC151, wherein the current operating power stateprioritizes increased performance over decreased power.

EC153) A method comprising:

-   -   in a device, receiving a power control command, and in response        modifying mapping information that enables mapping device power        management commands to corresponding operating power states of        the device, the modifying being based at least in part on        information provided by the power control command;    -   in the device, receiving an instance of a particular one of the        device power management commands, and in response accessing the        mapping information to determine a particular one of the        operating power states, the accessing being based at least in        part on the instance; and    -   in the device, in response to the accessing, operating the        device in accordance with the particular operating power state.

EC154) The method of EC153, wherein the device comprises a storagedevice and the acts of receiving are via an interface of the storagedevice that is compatible with at least one storage interface standard.

EC155) The method of EC153, wherein the device power management commandscomprise one or more of an IDLE command, a STANDBY command, and a SLEEPcommand.

EC156) The method of EC153, wherein the operating power states compriseone or more of a High Performance power state, an Active power state, aLow Power power state, an Idle power state, a Standby power state, and aSleep power state.

EC157) The method of EC153, wherein the power control command is asecond command, and further comprising:

-   -   in the storage device, receiving, before the receiving of the        second command, a first command via the interface; and    -   commencing processing of the second command while the first        command is outstanding.

EC158) The method of EC157, wherein the storage device comprisesnon-volatile memory, and the processing comprises altering what portionof the non-volatile memory is maximally enabled to be concurrentlyactive.

EC159) The method of EC158, wherein the non-volatile memory comprisesone or more flash memory devices, and the altering comprises alteringhow many of the flash memory devices are maximally enabled to beconcurrently active.

EC160) The method of EC157, wherein the storage device comprises one ormore interfaces to non-volatile memory, and the processing comprisesaltering what portion of the interfaces are maximally enabled to beconcurrently active.

EC161) A system comprising:

-   -   means for, in a device, receiving a power control command, and        in response modifying mapping information that enables mapping        device power management commands to corresponding operating        power states of the device, the modifying being based at least        in part on information provided by the power control command;    -   means for, in the device, receiving an instance of a particular        one of the device power management commands, and in response        accessing the mapping information to determine a particular one        of the operating power states, the accessing being based at        least in part on the instance; and    -   means for, in the device, and in response to the accessing,        operating the device in accordance with the particular operating        power state.

EC162) The system of EC161, wherein the device comprises a storagedevice and the commands are receivable via an interface of the storagedevice that is compatible with at least one storage interface standard.

EC163) The system of EC161, wherein the device power management commandscomprise one or more of an IDLE command, a STANDBY command, and a SLEEPcommand.

EC164) The system of EC161, wherein the operating power states compriseone or more of a High Performance power state, an Active power state, aLow Power power state, an Idle power state, a Standby power state, and aSleep power state.

EC165) The system of EC161, wherein the power control command is asecond command, and further comprising:

-   -   means for, in the storage device, receiving, before the        receiving of the second command, a first command via the        interface; and    -   means for commencing processing of the second command while the        first command is outstanding.

EC166) The system of EC165, wherein the storage device comprisesnon-volatile memory, and the processing comprises altering what portionof the non-volatile memory is maximally enabled to be concurrentlyactive.

EC167) The system of EC166, wherein the non-volatile memory comprisesone or more flash memory devices, and the altering comprises alteringhow many of the flash memory devices are maximally enabled to beconcurrently active.

EC168) The system of EC165, wherein the storage device comprises one ormore interfaces to non-volatile memory, and the processing comprisesaltering what portion of the interfaces are maximally enabled to beconcurrently active.

EC169) A non-transitory tangible computer readable medium having a setof instructions stored therein that when executed by a processingelement cause the processing element to perform and/or controloperations comprising:

-   -   in a device, receiving a power control command, and in response        modifying mapping information that enables mapping device power        management commands to corresponding operating power states of        the device, the modifying being based at least in part on        information provided by the power control command;    -   in the device, receiving an instance of a particular one of the        device power management commands, and in response accessing the        mapping information to determine a particular one of the        operating power states, the accessing being based at least in        part on the instance; and    -   in the device, in response to the accessing, operating the        device in accordance with the particular operating power state.

EC170) The non-transitory tangible computer readable medium of EC169,wherein the device comprises a storage device and the commands arereceivable via an interface of the storage device that is compatiblewith at least one storage interface standard.

EC171) The non-transitory tangible computer readable medium of EC169,wherein the device power management commands comprise one or more of anIDLE command, a STANDBY command, and a SLEEP command.

EC172) The non-transitory tangible computer readable medium of EC169,wherein the operating power states comprise one or more of a HighPerformance power state, an Active power state, a Low Power power state,an Idle power state, a Standby power state, and a Sleep power state.

EC173) The non-transitory tangible computer readable medium of EC169,wherein the power control command is a second command, and theoperations further comprise:

-   -   in the storage device, receiving, before the receiving of the        second command, a first command via the interface; and    -   commencing processing of the second command while the first        command is outstanding.

EC174) The non-transitory tangible computer readable medium of EC 173,wherein the storage device comprises non-volatile memory, and theprocessing comprises altering what portion of the non-volatile memory ismaximally enabled to be concurrently active.

EC175) The non-transitory tangible computer readable medium of EC174,wherein the non-volatile memory comprises one or more flash memorydevices, and the altering comprises altering how many of the flashmemory devices are maximally enabled to be concurrently active.

EC176) The non-transitory tangible computer readable medium of EC173,wherein the storage device comprises one or more interfaces tonon-volatile memory, and the processing comprises altering what portionof the interfaces are maximally enabled to be concurrently active.

EC177) An apparatus comprising:

-   -   logic circuitry enabled to receive, in a device, a power control        command, and in response modifying mapping information that        enables mapping device power management commands to        corresponding operating power states of the device, the        modifying being based at least in part on information provided        by the power control command;    -   logic circuitry enabled to receive, in the device, an instance        of a particular one of the device power management commands, and        in response accessing the mapping information to determine a        particular one of the operating power states, the accessing        being based at least in part on the instance; and    -   logic circuitry enabled to operate the device in response to the        accessing and in accordance with the particular operating power        state.

EC178) The apparatus of EC177, wherein the device comprises a storagedevice and the commands are receivable via an interface of the storagedevice that is compatible with at least one storage interface standard.

EC179) The apparatus of EC177, wherein the device power managementcommands comprise one or more of an IDLE command, a STANDBY command, anda SLEEP command.

EC180) The apparatus of EC177, wherein the operating power statescomprise one or more of a High Performance power state, an Active powerstate, a Low Power power state, an Idle power state, a Standby powerstate, and a Sleep power state.

EC181) The apparatus of EC177, wherein the power control command is asecond command, and further comprising:

-   -   logic circuitry enabled to receive, in the storage device and        before the receiving of the second command, a first command via        the interface; and    -   logic circuitry enabled to commence processing of the second        command while the first command is outstanding.

EC182) The apparatus of EC181, wherein the storage device comprisesnon-volatile memory, and the processing comprises altering what portionof the non-volatile memory is maximally enabled to be concurrentlyactive.

EC183) The apparatus of EC182, wherein the non-volatile memory comprisesone or more flash memory devices, and the altering comprises alteringhow many of the flash memory devices are maximally enabled to beconcurrently active.

EC184) The apparatus of EC1.81, wherein the storage device comprises oneor more interfaces to non-volatile memory, and the processing comprisesaltering what portion of the interfaces are maximally enabled to beconcurrently active.

EC185) Any of the foregoing ECs having or referring to power controlinformation, wherein the power control information specifies at leastone of an absolute power level and a relative power level.

EC186) Any of the foregoing ECs having or referring to an absolute powerlevel, wherein the absolute power level is any one of an average powerlevel and a maximum power level.

EC187) Any of the foregoing ECs having or referring to an absolute powerlevel, wherein the absolute power level is a maximum power level.

EC188) Any of the foregoing ECs having or referring to a relative powerlevel, wherein the relative power level specifies any one of a fractionless than one of a current power level and a multiplier greater than oneof a current power level.

EC189) Any of the foregoing ECs having or referring to a command,wherein the command is provided by a host.

EC190) Any of the foregoing ECs having or referring to first and secondcommands, wherein the first and the second commands are provided by ahost.

EC191) Any of the foregoing ECs having or referring to a host and astorage device, wherein the host is directly coupled to the storagedevice.

EC192) Any of the foregoing ECs having or referring to a host and astorage device, wherein the host is indirectly coupled to the storagedevice.

EC193) Any of the foregoing ECs having or referring to a host indirectlycoupled to a storage device, wherein the indirect coupling is at leastin part via any one or more of one or more expanders, one or moremultiplexors, and one or more intermediate controllers.

EC194) Any of the foregoing ECs having or referring to power controlinformation and a storage device, wherein at least a portion of thepower control information is persistent across a reset and/or a powercycle of the storage device.

EC195) Any of the foregoing ECs having or referring to an outstandingfirst command and a storage device, wherein the first command isoutstanding due to any one or more of

-   -   the first command is queued awaiting processing by the storage        device,    -   the storage device has not commenced processing of the first        command,    -   the storage device is processing the first command,    -   the storage device has not completed processing of the first        command,    -   response information associated with processing of the first        command is awaiting transmission by the storage device,    -   the storage device has not sent a response associated with the        first command, and    -   the first command has not been aborted.

EC196) Any of the foregoing ECs having or referring to persistent powercontrol information, wherein persistence of the persistent power controlinformation is unconditional.

EC 197) Any of the foregoing ECs having or referring to persistent powercontrol information, wherein persistence of the persistent power controlinformation is conditional.

EC 198) Any of the foregoing ECs having or referring to power controlinformation and persistent power control information, whereinpersistence of the persistent power control information is conditionalbased at least in part on some of the power control information.

EC199) Any of the foregoing ECs having or referring to persistent powercontrol information, wherein the persistence is at least in part viastorage to and/or retrieval from a mode page.

EC200) Any of the foregoing ECs having or referring to a mode page,wherein the mode page is a SCSI mode page.

EC201) Any of the foregoing ECs having or referring to power usageinformation, wherein the power usage information comprises one or morecurrent measurements. one or more power measurements, and/or one or moretemperature measurements.

EC202) Any of the foregoing ECs having or referring to predeterminedflash memory device power consumption information, wherein thepredetermined flash memory device power consumption informationcomprises per flash device type information.

EC203) Any of the foregoing ECs having or referring to predeterminedflash memory device power consumption information, wherein thepredetermined flash memory device power consumption informationcomprises per flash device vendor information.

EC204) Any of the foregoing ECs having or referring to one or moreinterfaces to non-volatile memory, wherein the interfaces tonon-volatile memory comprise at least one flash memory interface.

EC205) Any of the foregoing ECs having or referring to a referencefrequency generator, wherein the reference frequency generator comprisesone or more PLLs and/or one or more DLLs.

EC206) Any of the foregoing ECs having or referring to a storageinterface standard, wherein the storage interface standard comprises oneor more of

-   -   a Universal Serial Bus (USB) interface standard,    -   a Compact Flash (CF) interface standard,    -   a MultiMediaCard (MMC) interface standard,    -   an embedded MMC (eMMC) interface standard,    -   a Thunderbolt interface standard,    -   a UFS interface standard,    -   a Secure Digital (SD) interface standard,    -   a Memory Stick interface standard,    -   an xD-picture card interface standard,    -   an Integrated Drive Electronics (IDE) interface standard,    -   a Serial Advanced Technology Attachment (SATA) interface        standard,    -   an external SATA (eSATA) interface standard,    -   a Small Computer System Interface (SCSI) interface standard,    -   a Serial Attached Small Computer System Interface (SAS)        interface standard,    -   a Fibre Channel interface standard,    -   an Ethernet interface standard, and    -   a Peripheral Component Interconnect express (PCIe) interface        standard.

EC207) Any of the foregoing ECs having or referring to a flash memoryinterface, wherein the flash memory interface is compatible with one ormore of

-   -   an Open NAND Flash Interface (ONFI),    -   a Toggle-mode interface,    -   a Double-Data-Rate (DDR) synchronous interface,    -   a DDR2 synchronous interface,    -   a synchronous interface, and    -   an asynchronous interface.

EC208) Any of the foregoing ECs having or relating to a host, whereinthe host comprises one or more of

-   -   a computer,    -   a workstation computer,    -   a server computer,    -   a storage server,    -   a Storage Attached Network (SAN),    -   a Network Attached Storage (NAS) device,    -   a Direct Attached Storage (DAS) device,    -   a storage appliance,    -   a Personal Computer (PC),    -   a laptop computer,    -   a notebook computer,    -   a netbook computer.    -   a tablet device or computer,    -   an ultrabook computer,    -   an electronic reading device (an e-reader),    -   a Personal Digital Assistant (PDA),    -   a navigation system,    -   a (handheld) Global Positioning System (GPS) device,    -   an automotive control system,    -   an automotive media control system or computer,    -   a printer, copier or fax machine or all-in-one device,    -   a Point Of Sale (POS) device,    -   a cash-register,    -   a media player,    -   a television,    -   a media recorder,    -   a Digital Video Recorder (DVR),    -   a digital camera,    -   a cellular handset,    -   a cordless telephone handset, and    -   an electronic game.

EC209) Any of the foregoing ECs having or referring to a device, whereinthe device comprises a storage device.

EC210) Any of the foregoing ECs having or referring to a storage device,wherein the storage device comprises one or more of

-   -   an optical storage device,    -   a magnetic storage device,    -   a mechanical storage device, and    -   a solid-state storage device.

EC211) Any of the foregoing ECs having or referring to a storage device,wherein the storage device comprises one or more of

-   -   a disk drive,    -   a magnetic disk drive,    -   a solid-state disk drive,    -   a solid-state disk drive having one or more flash memories, and    -   a tape drive.

EC212) Any of the foregoing ECs having or referring to at least oneflash memory, wherein at least a portion of the at least one flashmemory comprises one or more of

-   -   NAND flash technology storage cells, and    -   NOR flash technology storage cells.

EC213) Any of the foregoing ECs having or referring to at least oneflash memory, wherein at least a portion of the at least one flashmemory comprises one or more of

-   -   Single-Level Cell (SLC) flash technology storage cells, and    -   Multi-Level Cell (MLC) flash technology storage cells.

EC214) Any of the foregoing ECs having or referring to at least oneflash memory, wherein at least a portion of the at least one flashmemory comprises one or more of

-   -   polysilicon technology-based charge storage cells, and    -   silicon nitride technology-based charge storage cells.

EC215) Any of the foregoing ECs having or referring to at least oneflash memory, wherein at least a portion of the at least one flashmemory comprises one or more of

-   -   two-dimensional technology-based flash memory technology, and    -   three-dimensional technology-based flash memory technology.

System

In some embodiments, a device, e.g. a storage device and/or an I/Odevice, such as an SSD, includes an SSD controller. The SSD controlleracts as a bridge between the host interface and NVM of the SSD, andexecutes commands of a host protocol sent from a computing host via ahost interface of the SSD. At least some of the commands direct the SSDto write and read the NVM with data sent from and to the computing host,respectively. In further embodiments, the SSD controller is enabled touse a map to translate between LBAs of the host protocol and physicalstorage addresses in the NVM. In further embodiments, at least a portionof the map is used for private storage (not visible to the computinghost) of the I/O device. For example, a portion of the LBAs notaccessible by the computing host is used by the I/O device to manageaccess to logs, statistics, or other private data.

In some embodiments, accessing compressed data of varying-sized quantain NVM provides improved storage efficiency in some usage scenarios. Forexample, an SSD controller receives (uncompressed) data from a computinghost (e.g., relating to a disk write command), compresses the data, andstores the compressed data into flash memory. In response to asubsequent request from the computing host (e.g., relating to a diskread command), the SSD controller reads the compressed data from theflash memory, uncompresses the compressed data, and provides theuncompressed data to the computing host. The compressed data is storedin the flash memory according to varying-sized quanta, the quanta sizevarying due to, e.g., compression algorithm, operating mode, andcompression effectiveness on various data. The SSD controlleruncompresses the data in part by consulting an included map table todetermine where header(s) are stored in the flash memory. The SSDcontroller parses the header(s) obtained from the flash memory todetermine where appropriate (compressed) data is stored in the flashmemory. The SSD controller uncompresses the appropriate data from theflash memory to produce the uncompressed data to provide to thecomputing host. In the instant application, uncompress (and variantsthereof) is synonymous with decompress (and variants thereof).

In various embodiments, an SSD controller includes a host interface forinterfacing with a computing host, an interface for interfacing with NVMsuch as flash memory, and circuitry for controlling the interfaces andperforming (and/or controlling various aspects of the performing)compressing and uncompressing, as well as lower-level redundancy and/orerror correction, higher-level redundancy and/or error correction, anddynamic higher-level redundancy mode management with independent siliconelements.

According to various embodiments, some host interfaces are compatiblewith one or more of a USB interface standard, a CF interface standard,an MMC interface standard, an eMMC interface standard, a Thunderboltinterface standard, a UFS interface standard, an SD interface standard,a Memory Stick interface standard, an xD-picture card interfacestandard, an IDE interface standard, a SATA interface standard, a SCSIinterface standard, a SAS interface standard, and a PCIe interfacestandard. According to various embodiments, the computing host is all orany portions of a computer, a workstation computer, a server computer, astorage server, a SAN, a NAS device, a DAS device, a storage appliance,a PC, a laptop computer, a notebook computer, a netbook computer, atablet device or computer, an ultrabook computer, an electronic readingdevice (such as an e-reader), a PDA, a navigation system, a (handheld)GPS device, an automotive control system, an automotive media controlsystem or computer, a printer, copier or fax machine or all-in-onedevice, a POS device, a cash-register, a media player, a television, amedia recorder, a DVR, a digital camera, a cellular handset, a cordlesstelephone handset, and an electronic game. In some embodiments, aninterfacing host (such as a SAS/SATA bridge) operates as a computinghost and/or as a bridge to a computing host.

In various embodiments, the SSD controller includes one or moreprocessors. The processors execute firmware to control and/or performoperation of the SSD controller. The SSD controller communicates withthe computing host to send and receive commands and/or status as well asdata. The computing host executes one or more of an operating system, adriver, and an application. Communication by the computing host with theSSD controller is optionally and/or selectively via the driver and/orvia the application. In a first example, all communication to the SSDcontroller is via the driver, and the application provides higher-levelcommands to the driver that the driver translates into specific commandsfor the SSD controller. In a second example, the driver implements abypass mode and the application is enabled to send specific commands tothe SSD controller via the driver. In a third example, a PCIe SSDcontroller supports one or more Virtual Functions (VFs), enabling anapplication, once configured, to communicate directly with the SSDcontroller, bypassing the driver.

According to various embodiments, some SSDs are compatible withform-factors, electrical interfaces, and/or protocols used by magneticand/or optical non-volatile storage, such as HDDs, CD drives, and DVDdrives. In various embodiments, SSDs use various combinations of zero ormore parity codes, zero or more RS codes, zero or more BCH codes, zeroor more Viterbi or other trellis codes, and zero or more LDPC codes.

FIG. 1A illustrates selected details of an embodiment of an SSDincluding an SSD controller enabled to perform device power control. TheSSD controller is for managing non-volatile storage, such as implementedvia NVM elements (e.g., flash memories). SSD Controller 100 iscommunicatively coupled via one or more External Interfaces 110 to ahost (not illustrated). According to various embodiments, ExternalInterfaces 110 are one or more of: a SATA interface; a SAS interface; aPCIe interface; a Fibre Channel interface; an Ethernet Interface (suchas 10 Gigabit Ethernet); a non-standard version of any of the precedinginterfaces; a custom interface; or any other type of interface used tointerconnect storage and/or communications and/or computing devices. Forexample, in some embodiments, SSD Controller 100 includes a SATAinterface and a PCIe interface.

SSD Controller 100 is further communicatively coupled via one or moreDevice Interfaces 190 to NVM 199 including one or more storage devices,such as one or more instances of Flash Device 192. According to variousembodiments, Device Interfaces 190 are one or more of: an asynchronousinterface; a synchronous interface; a single-data-rate (SDR) interface;a double-data-rate (DDR) interface; a DRAM-compatible DDR or DDR2synchronous interface; an ONFI compatible interface, such as an ONFI 2.2or ONFI 3.0 compatible interface; a Toggle-mode compatible flashinterface; a non-standard version of any of the preceding interfaces; acustom interface; or any other type of interface used to connect tostorage devices.

Each of Flash Device 192 has, in some embodiments, one or moreindividual Flash Die 194. According to type of a particular one of FlashDevice 192, a plurality of Flash Die 194 in the particular Flash Device192 is optionally and/or selectively accessible in parallel. FlashDevice 192 is merely representative of one type of storage deviceenabled to communicatively couple to SSD Controller 100. In variousembodiments, any type of storage device is usable, such as an SLC NANDflash memory, MLC NAND flash memory, NOR flash memory, flash memoryusing polysilicon or silicon nitride technology-based charge storagecells, two- or three-dimensional technology-based flash memory,read-only memory, static random access memory, dynamic random accessmemory, ferromagnetic memory, phase-change memory, racetrack memory,ReRAM, or any other type of memory device or storage medium.

According to various embodiments, Device Interfaces 190 are organizedas: one or more busses with one or more instances of Flash Device 192per bus; one or more groups of busses with one or more instances ofFlash Device 192 per bus, having busses in a group generally accessed inparallel; or any other organization of one or more instances of FlashDevice 192 onto Device Interfaces 190.

Continuing in FIG. 1A, SSD Controller 100 has one or more modules, suchas Host Interfaces 111. Data Processing 121, Buffer 131, Map 141,Recycler 151, ECC 161, Device Interface Logic 191, and CPU 171. Thespecific modules and interconnections illustrated in FIG. 1A are merelyrepresentative of one embodiment, and many arrangements andinterconnections of some or all of the modules, as well as additionalmodules not illustrated, are conceived. In a first example, in someembodiments, there are two or more Host Interfaces 111 to providedual-porting. In a second example, in some embodiments, Data Processing121 and/or ECC 161 are combined with Buffer 131. In a third example, insome embodiments, Host Interfaces 111 is directly coupled to Buffer 131,and Data Processing 121 optionally and/or selectively operates on datastored in Buffer 131. In a fourth example, in some embodiments, DeviceInterface Logic 191 is directly coupled to Buffer 131, and ECC 161optionally and/or selectively operates on data stored in Buffer 131.

Host Interfaces 111 sends and receives commands and/or data via ExternalInterfaces 110, and, in some embodiments, tracks progress of individualcommands via Tag Tracking 113. For example, the commands include a readcommand specifying an address (such as an LBA) and an amount of data(such as a number of LBA quanta, e.g., sectors) to read; in response theSSD provides read status and/or read data. For another example, thecommands include a write command specifying an address (such as an LBA)and an amount of data (such as a number of LBA quanta, e.g., sectors) towrite; in response the SSD provides write status and/or requests writedata and optionally subsequently provides write status. For yet anotherexample, the commands include a de-allocation command (e.g. a trimcommand) specifying one or more addresses (such as one or more LBAs)that no longer need be allocated; in response the SSD modifies the Mapaccordingly and optionally provides de-allocation status. In somecontexts an ATA compatible TRIM command is an exemplary de-allocationcommand. For yet another example, the commands include a super capacitortest command or a data hardening success query; in response, the SSDprovides appropriate status. In some embodiments, Host Interfaces 111 iscompatible with a SATA protocol and, using NCQ commands, is enabled tohave up to 32 pending commands, each with a unique tag represented as anumber from 0 to 31. In some embodiments. Tag Tracking 113 is enabled toassociate an external tag for a command received via External Interfaces110 with an internal tag used to track the command during processing bySSD Controller 100.

According to various embodiments, one or more of: Data Processing 121optionally and/or selectively processes some or all data sent betweenBuffer 131 and External Interfaces 110; and Data Processing 121optionally and/or selectively processes data stored in Buffer 131. Insome embodiments, Data Processing 121 uses one or more Engines 123 toperform one or more of: formatting; reformatting; transcoding; and anyother data processing and/or manipulation task.

Buffer 131 stores data sent to/from External Interfaces 110 from/toDevice Interfaces 190. In some embodiments, Buffer 131 additionallystores system data, such as some or all map tables, used by SSDController 100 to manage one or more instances of Flash Device 192. Invarious embodiments, Buffer 131 has one or more of: Memory 137 used fortemporary storage of data; DMA 133 used to control movement of data toand/or from Buffer 131; and ECC-X 135 used to provide higher-level errorcorrection and/or redundancy functions; and other data movement and/ormanipulation functions. An example of a higher-level redundancy functionis a RAID-like capability (e.g. RASIE), with redundancy at a flashdevice level (e.g., multiple ones of Flash Device 192) and/or a flashdie level (e.g., Flash Die 194) instead of at a disk level.

According to various embodiments, one or more of: ECC 161 optionallyand/or selectively processes some or all data sent between Buffer 131and Device Interfaces 190; and ECC 161 optionally and/or selectivelyprocesses data stored in Buffer 131. In some embodiments, ECC 161 isused to provide lower-level error correction and/or redundancyfunctions, such as in accordance with one or more ECC techniques. Insome embodiments, ECC 161 implements one or more of: a CRC code; aHamming code; an RS code; a BCH code; an LDPC code; a Viterbi code; atrellis code; a hard-decision code; a soft-decision code; anerasure-based code; any error detecting and/or correcting code; and anycombination of the preceding. In some embodiments, ECC 161 includes oneor more decoders (such as LDPC decoders).

Device Interface Logic 191 controls instances of Flash Device 192 viaDevice Interfaces 190. Device Interface Logic 191 is enabled to senddata to/from the instances of Flash Device 192 according to a protocolof Flash Device 192. Device Interface Logic 191 includes Scheduling 193to selectively sequence control of the instances of Flash Device 192 viaDevice Interfaces 190. For example, in some embodiments, Scheduling 193is enabled to queue operations to the instances of Flash Device 192, andto selectively send the operations to individual ones of the instancesof Flash Device 192 (or Flash Die 194) as individual ones of theinstances of Flash Device 192 (or Flash Die 194) are available.

Map 141 converts between data addressing used on External Interfaces 110and data addressing used on Device Interfaces 190, using Table 143 tomap external data addresses to locations in NVM 199. For example, insome embodiments, Map 141 converts LBAs used on External Interfaces 110to block and/or page addresses targeting one or more Flash Die 194, viamapping provided by Table 143. For LBAs that have never been writtensince drive manufacture or de-allocation, the Map points to a defaultvalue to return if the LBAs are read. For example, when processing ade-allocation command, the Map is modified so that entries correspondingto the de-allocated LBAs point to one of the default values. In variousembodiments, there are various default values, each having acorresponding pointer. The plurality of default values enables readingsome de-allocated LBAs (such as in a first range) as one default value,while reading other de-allocated LBAs (such as in a second range) asanother default value. The default values, in various embodiments, aredefined by flash memory, hardware, firmware, command and/or primitivearguments and/or parameters, programmable registers, or variouscombinations thereof.

In some embodiments, Map 141 uses Table 143 to perform and/or to look uptranslations between addresses used on External Interfaces 110 and dataaddressing used on Device Interfaces 190. According to variousembodiments, Table 143 is one or more of: a one-level map; a two-levelmap; a multi-level map; a map cache; a compressed map; any type ofmapping from one address space to another; and any combination of theforegoing. According to various embodiments, Table 143 includes one ormore of: static random access memory; dynamic random access memory; NVM(such as flash memory); cache memory; on-chip memory; off-chip memory;and any combination of the foregoing.

In some embodiments, Recycler 151 performs garbage collection. Forexample, in some embodiments, instances of Flash Device 192 containblocks that must be erased before the blocks are re-writeable. Recycler151 is enabled to determine which portions of the instances of FlashDevice 192 are actively in use (e.g., allocated instead ofde-allocated), such as by scanning a map maintained by Map 141, and tomake unused (e.g., de-allocated) portions of the instances of FlashDevice 192 available for writing by erasing the unused portions. Infurther embodiments, Recycler 151 is enabled to move data stored withininstances of Flash Device 192 to make larger contiguous portions of theinstances of Hash Device 192 available for writing.

In some embodiments, instances of Flash Device 192 are selectivelyand/or dynamically configured, managed, and/or used to have one or morebands for storing data of different types and/or properties. A number,arrangement, size, and type of the bands are dynamically changeable. Forexample, data from a computing host is written into a hot (active) band,while data from Recycler 151 is written into a cold (less active) band.In some usage scenarios, if the computing host writes a long, sequentialstream, then a size of the hot band grows, whereas if the computing hostdoes random writes or few writes, then a size of the cold band grows.

CPU 171 controls various portions of SSD Controller 100. CPU 171includes CPU Core 172. CPU Core 172 is, according to variousembodiments, one or more single-core or multi-core processors. Theindividual processors cores in CPU Core 172 are, in some embodiments,multi-threaded. CPU Core 172 includes instruction and/or data cachesand/or memories. For example, the instruction memory containsinstructions to enable CPU Core 172 to execute programs (e.g. softwaresometimes called firmware) to control SSD Controller 100. In someembodiments, some or all of the firmware executed by CPU Core 172 isstored on instances of Flash Device 192 (as illustrated, e.g., asFirmware 106 of NVM 199 in FIG. 18).

In various embodiments, CPU 171 further includes: Command Management 173to track and control commands received via External Interfaces 110 whilethe commands are in progress; Buffer Management 175 to controlallocation and use of Buffer 131; Translation Management 177 to controlMap 141; Coherency Management 179 to control consistency of dataaddressing and to avoid conflicts such as between external data accessesand recycle data accesses; Device Management 181 to control DeviceInterface Logic 191; Identity Management 182 to control modification andcommunication of identify information; Power Control 183 to controldevice power control operations; and optionally other management units.None, any, or all of the management functions performed by CPU 171 are,according to various embodiments, controlled and/or managed by hardware,by software (such as firmware executing on CPU Core 172 or on a hostconnected via External Interfaces 110), or any combination thereof.

In some embodiments, CPU 171 is enabled to perform other managementtasks, such as one or more of: gathering and/or reporting performancestatistics; implementing SMART; controlling power sequencing,controlling and/or monitoring and/or adjusting power consumption;responding to power failures; controlling and/or monitoring and/oradjusting clock rates; and other management tasks.

Various embodiments include a computing-host flash memory controllerthat is similar to SSD Controller 100 and is compatible with operationwith various computing hosts, such as via adaptation of Host Interfaces111 and/or External Interfaces 110. The various computing hosts includeone or any combination of a computer, a workstation computer, a servercomputer, a storage server, a SAN, a NAS device, a DAS device, a storageappliance, a PC, a laptop computer, a notebook computer, a netbookcomputer, a tablet device or computer, an ultrabook computer, anelectronic reading device (such as an e-reader), a PDA, a navigationsystem, a (handheld) GPS device, an automotive control system, anautomotive media control system or computer, a printer, copier or faxmachine or all-in-one device, a POS device, a cash-register, a mediaplayer, a television, a media recorder, a DVR, a digital camera, acellular handset, a cordless telephone handset, and an electronic game.

In various embodiments, all or any portions of an SSD controller (or acomputing-host flash memory controller) are implemented on a single IC,a single die of a multi-die IC, a plurality of dice of a multi-die IC,or a plurality of ICs. For example, Buffer 131 is implemented on a samedie as other elements of SSD Controller 100. For another example, Buffer131 is implemented on a different die than other elements of SSDController 100.

FIG. 1B illustrates selected details of various embodiments of systemsincluding one or more instances of the SSD of FIG. 1A coupled (directlyor indirectly) to a host that is enabled to operate with device powercontrol. SSD 101 includes SSD Controller 100 coupled to NVM 199 viaDevice Interfaces 190. The figure illustrates various classes ofembodiments: a single SSD coupled directly to a host, a plurality ofSSDs each respectively coupled directly to a host via respectiveexternal interfaces, and one or more SSDs coupled indirectly to a hostvia various interconnection elements.

As an example embodiment of a single SSD coupled directly to a host, oneinstance of SSD 101 is coupled directly to Host 102 via ExternalInterfaces 110 (e.g. Switch/Fabric/Intermediate Controller 103 isomitted, bypassed, or passed-through). As an example embodiment of aplurality of SSDs each coupled directly to a host via respectiveexternal interfaces, each of a plurality of instances of SSD 101 isrespectively coupled directly to Host 102 via a respective instance ofExternal Interfaces 110 (e.g. Switch/Fabric/Intermediate Controller 103is omitted, bypassed, or passed-through). As an example embodiment ofone or more SSDs coupled indirectly to a host via variousinterconnection elements, each of one or more instances of SSD 101 isrespectively coupled indirectly to Host 102. Each indirect coupling isvia a respective instance of External Interfaces 110 coupled toSwitch/Fabric/Intermediate Controller 103, and Intermediate Interfaces104 coupling to Host 102.

Some of the embodiments including Switch/Fabric/Intermediate Controller103 also include Card Memory 112C coupled via Memory Interface 180 andaccessible by the SSDs. In various embodiments, one or more of the SSDs,the Switch/Fabric/Intermediate Controller, and/or the Card Memory areincluded on a physically identifiable module, card, or pluggable element(e.g. I/O Card 116). In some embodiments, SSD 101 (or variationsthereof) corresponds to a SAS drive or a SATA drive that is coupled toan initiator operating as Host 102.

Host 102 is enabled to execute various elements of Host Software 115,such as various combinations of OS 105, Driver 107, Power ControlSoftware 108, Application 109, and Multi-Device Management Software 114.Dotted-arrow 107D is representative of Host Software ←→ I/O DeviceCommunication, e.g. data sent/received to/from one or more of theinstances of SSD 101 and from/to any one or more of OS 105 via Driver107, Driver 107, and Application 109, either via Driver 107, or directlyas a VF.

OS 105 includes and/or is enabled to operate with drivers (illustratedconceptually by Driver 107) for interfacing with the SSD. Variousversions of Windows (e.g. 95, 98, ME, NT, XP, 2000, Server, Vista, and7), various versions of Linux (e.g. Red Hat, Dehian, and Ubuntu), andvarious versions of MacOS (e.g. 8, 9 and X) are examples of OS 105. Invarious embodiments, the drivers are standard and/or generic drivers(sometimes termed “shrink-wrapped” or “pre-installed”) operable with astandard interface and/or protocol such as SATA, AHCI, or NVM Express,or are optionally customized and/or vendor-specific to enable use ofcommands specific to SSD 101. Some drives and/or drivers havepass-through modes to enable application-level programs, such asApplication 109 via Optimized NAND Access (sometimes termed ONA) orDirect NAND Access (sometimes termed DNA) techniques, to communicatecommands directly to SSD 101, enabling a customized application to usecommands specific to SSD 101 even with a generic driver. ONA techniquesinclude one or more of: use of non-standard modifiers (hints); use ofvendor-specific commands; communication of non-standard statistics, suchas actual NVM usage according to compressibility; and other techniques.DNA techniques include one or more of: use of non-standard commands orvendor-specific providing unmapped read, write, and/or erase access tothe NVM; use of non-standard or vendor-specific commands providing moredirect access to the NVM, such as by bypassing formatting of data thatthe I/O device would otherwise do; and other techniques. Examples of thedriver are a driver without ONA or DNA support, an ONA-enabled driver, aDNA-enabled driver, and an ONA/DNA-enabled driver. Further examples ofthe driver are a vendor-provided, vendor-developed, and/orvendor-enhanced driver, and a client-provided, client-developed, and/orclient-enhanced driver.

Examples of the application-level programs are an application withoutONA or DNA support, an ONA-enabled application, a DNA-enabledapplication, and an ONA/DNA-enabled application. Dotted-arrow 109D isrepresentative of Application ←→ I/O Device Communication (e.g. bypassvia a driver or bypass via a VF for an application), e.g. an ONA-enabledapplication and an ONA-enabled driver communicating with an SSD, such aswithout the application using the OS as an intermediary. Dotted-arrow109V is representative of Application ←→ I/O Device Communication (e.g.bypass via a VF for an application), e.g. a DNA-enabled application anda DNA-enabled driver communicating with an SSD, such as without theapplication using the OS or the driver as intermediaries.

Power Control Software 108 is conceptually representative of variousembodiments implementing all or any portions of a command source agentvia any combination of one or more stand alone software modules, OS 105,Driver 107, and/or Application 109.

One or more portions of NVM 199 are used, in some embodiments, forfirmware storage, e.g. Firmware 106. The firmware storage includes oneor more firmware images (or portions thereof). A firmware image has, forexample, one or more images of firmware, executed, e.g., by CPU Core 172of SSD Controller 100. A firmware image has, for another example, one ormore images of constants, parameter values, and NVM device information,referenced, e.g. by the CPU core during the firmware execution. Theimages of firmware correspond, e.g., to a current firmware image andzero or more previous (with respect to firmware updates) firmwareimages. In various embodiments, the firmware provides for generic,standard, ONA, and/or DNA operating modes. In some embodiments, one ormore of the firmware operating modes are enabled (e.g. one or more APIsare “unlocked”) via keys or various software techniques, optionallycommunicated and/or provided by a driver.

In some embodiments, one or more portions of NVM 199 are used fornon-volatile storage of power mode and/or control information, e.g.Saved Power Mode 196. Alternatively, non-volatile storage of power modeand/or control information is implemented via one or more portions ofFirmware 106, such as via one or more images of manufacturing and/oroperating power control constants, variables, indicators, and/orparameters.

In some embodiments lacking the Switch/Fabric/Intermediate Controller,the SSD is coupled to the Host directly via External Interfaces 110. Invarious embodiments, SSD Controller 100 is coupled to the Host via oneor more intermediate levels of other controllers, such as a RAIDcontroller. In some embodiments, SSD 101 (or variations thereof)corresponds to a SAS drive or a SATA drive andSwitch/Fabric/Intermediate Controller 103 corresponds to an expanderthat is in turn coupled to an initiator, or alternativelySwitch/Fabric/Intermediate Controller 103 corresponds to a bridge thatis indirectly coupled to an initiator via an expander. In someembodiments, Switch/Fabric/Intermediate Controller 103 includes one ormore PCIe switches and/or fabrics.

In various embodiments, such as some of the embodiments with Host 102 asa computing host (e.g. a computer, a workstation computer, a servercomputer, a storage server, a SAN, a NAS device, a DAS device, a storageappliance, a PC, a laptop computer, a notebook computer, and/or anetbook computer), the computing host is optionally enabled tocommunicate (e.g. via optional I/O & Storage Devices/Resources 117 andoptional LAN/WAN 119) with one or more local and/or remote servers (e.g.optional Servers 118). The communication enables, for example, localand/or remote access, management, and/or usage of any one or more of SSD101 elements. In some embodiments, the communication is wholly orpartially via Ethernet. In some embodiments, the communication is whollyor partially via Fibre Channel. LAN/WAN 119 is representative, invarious embodiments, of one or more Local and/or Wide Area Networks,such as any one or more of a network in a server farm, a networkcoupling server farms, a metro-area network, and the Internet.

In various embodiments, an SSD controller and/or a computing-host flashmemory controller in combination with one or more NVMs are implementedas a non-volatile storage component, such as a USB storage component, aCF storage component, an MMC storage component, an eMMC storagecomponent, a Thunderbolt storage component, a UFS storage component, anSD storage component, a Memory Stick storage component, and anxD-picture card storage component.

In various embodiments, all or any portions of an SSD controller (or acomputing-host flash memory controller), or functions thereof, areimplemented in a host that the controller is to be coupled with (e.g.,Host 102 of FIG. 1B). In various embodiments, all or any portions of anSSD controller (or a computing-host flash memory controller), orfunctions thereof, are implemented via hardware (e.g., logic circuitry),software and/or firmware (e.g., driver software and/or SSD controlfirmware), or any combination thereof. For example, functionality of orassociated with an ECC unit (such as similar to ECC 161 and/or ECC-X 135of FIG. 1A) is implemented partially via software on a host andpartially via a combination of firmware and hardware in an SSDcontroller. For another example, functionality of or associated with arecycler unit (such as similar to Recycler 151 of FIG. 1A) isimplemented partially via software on a host and partially via hardwarein a computing-host flash memory controller.

Device Power Control Operation

FIG. 2 illustrates selected details of various embodiments of devicepower control. The illustrated actions are performed variously by a host(e.g. Host 102 of FIG. 1B) as illustrated by a dashed-box in theleft-hand portion of the figure (Host Actions 200H) and a device (e.g.an instance of SSD 101 of FIG. 1B) as illustrated by the dashed-box inthe center and right-hand portions of the figure (Device Actions 200D).The host is coupled to and/or in communication with the device (e.g. asillustrated by Intermediate Interfaces 104 and optionallySwitch/Fabric/Intermediate Controller 103 of FIG. 1B).

In the figure, time conceptually increases from top to bottom. Forexample, 212D, 213D, 214D, 215D, and 216D occur at respectively latertimes. For yet another example, dotted-line boxes 213D, 214D, 215D, and216D are conceptually representative of an action that is performed,according to various embodiments, usage scenarios, and/or circumstances,before (213D and 214D), wholly or partially overlapping with (215D), orafter (216D) 204D.

The following description of operation is in a context of two commands,to simplify explanation. One of the commands (the second) is a powercontrol command, and the other one of the commands (the first) is acommand that is not a power control command, e.g. a read or a writecommand. Other operating contexts occur where there are a multiplicityof commands, some being power control commands, and others beingcommands that are not power control commands. Operation in the otheroperating contexts are similar to the described operation, such as whenconsidering the multiplicity of commands as overlapping windows of pairsof commands, e.g. first and second commands as described following. Insummary, a power control command is sent from a host to a device andthen processed, at least in some circumstances, before commands sentbefore the sending of the power control command are processed (e.g. thepower control command is processed “out-of-order” with respect topreviously sent commands).

More specifically, the actions begin (Start 201H). A host sends a firstcommand (that is not a power control command) to a device (Issue (otherthan) Power Control Command 202H). In response, the device accepts thefirst command (Receive (other than) Power Control Command 212D), andperforms operations in accordance with the first command (Process (otherthan) Power Control Command 213D, 214D, 2150, and 216D). Processing ofthe first command is then complete (End 299D). After sending the firstcommand to the device, the host sends a second command (that is a powercontrol command) to the device (Issue Power Control Command 203H). Thesecond command is generated, for example, via execution of one or morepower control software modules (e.g. all or any portions of PowerControl Software 108 of FIG. 1B). In response, the device accepts thesecond command (Receive Power Control Command 203D), and immediatelyperforms operations in accordance with the second command (Process PowerControl Command 2040). Processing of the second command is then complete(End 299D).

In various embodiments, usage scenarios, and/or circumstances, theprocessing of the second command is variously entirely complete,partially complete, and not begun before the processing of the firstcommand begins. For example, as illustrated conceptually by 216D, theprocessing of the power control command is entirely complete before theprocessing of the (other than) power control command begins. E.g. the(other than) power control command remains outstanding (such as remainsqueued) while the power control command is entirely processed. Foranother example, as illustrated conceptually by 215D, the processing ofthe power control command is entirely or partially concurrent with theprocessing of the (other than) power control command. For yet anotherexample, as illustrated conceptually by 213D and 214D, the processing ofthe power control command is not begun before the processing of the(other than) power control command begins, continues, and/or completes.Thus, processing of the power control command begins, continues, andcompletes independently and irrespectively of the processing of the(other than) power control command.

In some embodiments, the power control command is a queued command andis performed without delay by the device. In some embodiments, the powercontrol command is a queued command and is performed in any order (e.g.with respect to other queued commands) that is convenient to and/ordetermined by the device (e.g. to improve performance and/or to reducepower).

In various embodiments, the power control command is issued in responseto execution of one or more programs or portions thereof on the host.For example, a user invokes a power control program (e.g. Application109 of FIG. 1B) with a directive to set power to a default setting. Foryet another example, a device driver (e.g. Driver 107 of FIG. 1B)determines, such as due to inactivity and/or temperature overage, thatpower is to be reduced, and issues a power control command to reducepower. For yet another example, an OS (e.g. OS 105 of FIG. 1B) orportion thereof determines, such as due to expected performancerequirements, that power is to be increased (or at least allowed toincrease), and issues a power control command to increase power.

FIG. 3 illustrates selected details of various embodiments of devicepower control persistence. The illustrated actions are performed by adevice (e.g. an instance of SSD 101 of FIG. 1B). The actions arevariously in response to commands sent by a host (e.g. Host 102 of FIG.1B), stimuli that is external to the device (e.g. application of powerand/or a request for reset), and operation of the device (e.g.processing a command). In summary, a power control command is sent froma host to a device. The power control command is optionally and/orselectively effective until a next power up, until a next reset, and/oruntil a next power control command.

More specifically, the actions begin (Start 301). In response to adownload firmware command, a firmware image is downloaded and madeavailable for execution (Install FW 302). The firmware image includesstorage of a saved power mode indicating the power mode that the deviceis to operate in accordance with subsequent to the next power up and/orreset of the device. Manufacturing of the firmware image includessetting the saved power mode to indicate an initial power mode suitablefor first power up and/or reset of the device(SavedPowerMode<=ManufacturingPowerMode 312).

Subsequently, in response to a first power up and/or reset event of thedevice (PowerUp/Reset 302U), an operating power mode indicator is set toa value (Initialize 303) identical to the saved power mode(OperatingPowerMode<=SavedPowerMode 313). As this is the first power upand/or reset of the device, the saved power mode is a value that was setby the manufacturing, and thus the operating power mode indicator is setto the manufacturing value. The device completes operations performed inresponse to the power up and/or reset and begins operating in accordancewith the operating power mode indicator (Operate 304). For example, ifthe manufacturing value was “80%”, then the device begins operating at80% of a maximum power budget.

The device continues to operate in accordance with the operating powermode indicator (processing, e.g., read and/or write commands) until acommand that affects power control is received by the device (PowerControl Command 304P) or a power up and/or reset of the device occurs(PowerUp/Reset 304U). In response to receiving a power control command,the device computes a new power mode and determines if the power controlcommand (and/or one or more optional parameters associated with thepower control command) specifies a temporary change to operating powermode or a “permanent” change in the operating power mode (Persistent?305). A temporary change corresponds to a change that remains in effectuntil a subsequent power cycle and/or reset of the device. A permanentchange corresponds to a change that remains in effect until a subsequentpower control command, and “persists” across one or more power cyclesand/or resets of the device.

If the change is determined to be permanent (Yes 305Y), then informationdescribing the new operating mode is stored for later reference (ChangeSaved 306), such as by setting the saved power mode to indicate anappropriate value (SavedPowerMode<=NewPowerMode 316). Flow then proceedsto alter the operating power mode indicator (Change Operating 307)according to the new power mode (OperatingPowerMode<=NewPowerMode 317).

If the change is determined to be temporary (No 305N), then flowproceeds directly to alter the operating power mode indicator (ChangeOperating 307) according to the new power mode(OperatingPowerMode<=NewPowerMode 317), without altering the saved powermode.

After the altering of the operating power mode indicator (whether inresponse to a permanent or a temporary change), the flow returns tocontinue to operate in accordance with the (now changed) operating powermode indicator (Operate 304). As after 303, the device continues tooperate in accordance with the operating power mode indicator(processing, e.g., read and/or write commands) until a command thataffects power control is received by the device (Power Control Command304P) or a power up and/or reset of the device occurs (PowerUp/Reset304U). In response to a power up and/or a reset (PowerUp/Reset 304U),the flow returns to set the operating power mode indicator to a value(Initialize 303) identical to the saved power mode(OperatingPowerMode<=SavedPowerMode 313). If there have been one or morepower control commands specifying a permanent change, then the savedpower mode has been determined at least in part by the most recent ofthe power control commands specifying a permanent change, and theoperating power mode indicator is set according to the most recent ofthe power control commands specifying a permanent change. Thus theeffect of the most recent of the power control commands specifying apermanent change persists across the power up and/or reset of thedevice.

In some embodiments, one or more of the power control commands are“absolute”, e.g., “set power mode to 80%” or “set power mode to 100%”.In some embodiments, one or more of the absolute power control commandsare with respect to a maximum, e.g., a maximum power budget for a deviceor a maximum power dissipation allowable for a device. Thus in responseto the absolute power control command “set power mode to 80%”, the savedpower mode is set to indicate 80%, resulting in operation at 80% of amaximum power budget, or alternatively operation at 80% of a maximumpower dissipation. In some embodiments, one or more of the absolutepower control commands are with respect to an average, e.g. an averagepower budget for a device or an average power dissipation allowable fora device. Thus in response to the absolute power control command “setpower mode to 80%”, the saved power mode is set to indicate 80%,resulting in operation at 80% of an average power budget, oralternatively operation at 80% of an average power dissipation.

In some embodiments, one or more of the power control commands are“relative”, e.g., “reduce power mode by 10%” and “set power to 90% ofcurrent power”. For a first example. a device is operating at 80% of amaximum power budget. Then a relative power control command “reducepower mode by 10%” is received. In response, the saved power mode is setto indicate 70%, resulting in operation at 70% of the maximum powerbudget. For a second example, the device is operating at 80% of themaximum power budget. Then a relative power control command “set powerto 90% of current power” is received. In response, the saved power modeis set to indicate 72%, resulting in operation at 72% of the maximumpower budget. For a third example, the device is operating at 90% of themaximum power budget. Then a relative power control command “set powerto 1.1 times current power” is received. In response, the saved powermode is set to indicate 99%, resulting in operation at 99% of themaximum power budget.

In some embodiments, a power control command (and/or one or moreoptional parameters associated with the power control command) specifiesa new operating power mode as well as a conceptual “timeline” that thenew operating power mode is applicable to. The aforementioned temporaryand permanent specifications are examples of the conceptual timeline.Other specifications include any one or more of “persistent across areset but not a power cycle”, “effective at a next power cycle” and“effective at a next reset”.

In various embodiments, effecting operation at various power levels isperformed by various techniques, such as increasing/reducing concurrentactivity and/or frequency. For example, reducing a maximum number ofactive flash devices reduces power consumption (e.g. reducing how manyinstances of Flash Device 192 and/or of Flash Die 194 of FIG. 1A areallowed to operate concurrently). For another example, increasing anallowed maximum concurrent activity on one or more device interfacebuses increases power consumption (e.g. increasing a maximum allowedwidth of data transmission for Device Interfaces 190 of FIG. 1A). Foryet another example, increasing/reducing a frequency of operation of aprocessing clement of the device increases/reduces power consumption(e.g. increasing/reducing an operating and/or output frequency of a PLLand/or a DLL coupled to CPU 171 of FIG. 1A).

In various embodiments, the saved power mode is stored in non-volatilememory, such as illustrated conceptually by Saved Power Mode 196 of FIG.1B. In various embodiments, the saved power mode and/or a manufacturingvalue thereof is stored as part of a firmware image, such as illustratedconceptually by Firmware 106 of FIG. 1B. In various embodiments, thesaved power mode and/or a representation thereof is stored and/orreceived from an implementation of a mode page, e.g. a SCSI mode page asimplemented by all or any portion of Saved Power Mode 196.

In various embodiments, all or any portions of one or more elementsillustrated in FIG. 3 (and/or related to same), correspond to all or anyportions of one or more elements illustrated in FIG. 2. For example,304P of FIG. 3 corresponds to 203H of FIG. 2. For another example, anyone or more of 305, 306, 316, 307, and 317 collectively correspond toall or any portions of 204D of FIG. 2.

FIG. 4 illustrates selected details of various embodiments of devicepower control collection and distribution. Similar to FIG. 2, theillustrated actions are performed variously by a host (e.g. Host 102 ofFIG. 1B) as illustrated by a dashed-box in the left-hand portion of thefigure (Host Actions 400H) and a device (e.g. an instance of SSD 101 ofFIG. 1B) as illustrated by the clashed-box in the center and right-handportions of the figure (Device Actions 400D). The host is coupled toand/or in communication with the device (e.g. as illustrated byIntermediate Interfaces 104 and optionally Switch/Fabric/IntermediateController 103 of FIG. 1B). In summary, a power control command toobtain power information is sent to a device and distributed by thedevice to other devices as appropriate. Results of the command areobtained from the device and the other devices as appropriate andreturned to the host. The host, at least in part based on the results,optionally and/or selectively sends a power control command to changepower to the device. The device then distributes the command to theother devices as appropriate and processes the command itself.

More specifically, the actions begin (Start 401H). A host sends a typeof power control command, specifically a power information collectioncommand to collect information relating to power consumption and/oroperating temperatures (Issue Power Control Command (Info Collection)402H). In response, the device accepts the command (Receive PowerControl Command (Info Collection) 402D). Then the device determines ifthe command is to be sent to one or more other devices (ConditionallyDistribute 403D), and if so, sends the command to the other devices((To) Other Devices 413D). For example, if the devices are arranged in atree and the instant device is a leaf node of the tree, then the instantdevice performs no distribution. If the instant device is not a leafnode, then the instant device sends the command to any of the otherdevices coupled to the instant device. Each of the other devices thatare sent the command by the instant device performs in accordance with400D, including sending the command to other devices as appropriate.Thus the command is eventually sent to all of the devices.

Then the (instant) device gathers results of the power informationcollection command and returns the results to the host (Collect Results404D). The gathering includes obtaining results from itself, as well asthe other devices (if any) that ultimately received the command ((From)Other Devices 414D). For example, if the instant device is the onlydevice (or alternatively is a leaf device of a tree of devices), thenthe gathering is only of results of the instant device. For anotherexample, if the instant device is a root device of a tree of devices,then the gathering is of results of all of the devices of the tree.

In response to the results, the host determines a new power operatingpoint (Determine Revised Power Plan 404H). The host then sends anothertype of power control command, specifically a power change controlcommand to modify the power operation of the devices (Issue PowerControl Command (Change) 405H). In response, the device accepts thepower change control command (Receive Power Control Command (Change)405D). Then the device determines (as in 403D) if the command is to besent to the (if any) other devices (Conditionally Distribute 406D), andif so, sends the command to the other devices ((To) Other Devices 416D).Further (as with respect to 403D), the command is eventually sent to allof the devices. Then the (instant) device processes the command itself(Perform 407D). Actions are then complete (End 499D).

In various embodiments, the results are expressed as any one or more ofone or more current measurements (e.g. in milliamps), power measurements(e.g. in milliwatts), temperature measurements, and/or approximationsthereof. In various embodiments, one or more of the results representrecent information, e.g. obtained in response to the power informationcollection command, and/or past information, e.g. obtained from amonitoring activity such as stored in a log. In various embodiments, oneor more of the results are one or more averages, maxima, and minima overa specific time interval and or one or more specific physical regions.For example, a result is an average of a plurality of sensors on acircuit board of a device, and the average is further averaged overtime, e.g., a most recent minute. in some embodiments, a device (atleast conceptually) includes a plurality of sub-devices, and the resultscorrespond to one or more averages, maxima, and minima across thesub-devices.

In some embodiments, the host determines the new power operating point(e.g. as in 404H) at least in part with an objective to manage any oneor more of current usage, power consumption, and/or temperature.

In various embodiments, all or any portions of one or more elementsillustrated in FIG. 4 (and/or related to same), correspond to all or anyportions of one or more elements illustrated in FIG. 2 and/or FIG. 3.For example, 402H and/or 405H of FIG. 4 correspond to instances of 203Hof FIG. 2. For another example, 402D and/or 405D of FIG. 4 correspond toinstances of 203D of FIG. 2. For yet another example, any one or more of403D, 413D, 404D, and 414D of FIG. 4 collectively correspond to all orany portions of 204D of FIG. 2. For yet another example, any one or moreof 406D, 416D, and 407D of FIG. 4 collectively correspond to all or anyportions of 204D of FIG. 2. For yet another example, 407D of FIG. 4corresponds to any one or more of all or any portions of 305, 306, 316,307, and 317 of FIG. 3.

FIG. 5 illustrates selected details of various embodiments of devicepower control of an interface. The illustrated actions are performed byan interface (e.g. of a device and for communication with a host) and/orone or more elements controlling and/or managing the interface (such asHost Interfaces 111 of FIG. 1A).

In summary, the interface is a portion of a device and is a physicalinterface such as a PHY interface optionally and/or selectivelycompatible with one or more storage interface standards. While operatingin a compatible mode, the PHY interface is fully compliant with aparticular storage interface standard (e.g. a SATA interface standard).While operating in an enhanced mode, the PHY interface is fullycompliant with the particular storage interface standard except withregards to processing requests to transition operation to a specificpower mode. While operating in the enhanced mode, the requests areprocessed conditionally and/or selectively dependent on a power state ofthe device, and a request to transition to a particular power modeconditionally and/or selectively results in operation in the particularpower mode, another power mode that is different than the particularpower mode, or continued operation in a current power mode.

More specifically, action begins in response to powering up and/orresetting the interface (PowerUp/Reset 501). The interface theninitializes, including setting a beginning operating power mode for theinterface (Initialize PHY Power Mode 502). Subsequently the interfaceoperates in accordance with the beginning operating power mode (OperatePHY 503). The interface continues to operate in accordance with thebeginning operating power mode until receipt of a request to change to aspecific power mode (Transition Request 503R). The request is receivedvia the interface, such as from a host coupled to the device via theinterface (e.g. from Host 102 of FIG. 1B to SSD Controller 100 via HostInterfaces 111 of FIG. 1A).

Then the device consults information concerning current operating powerstate of the device (Examine Device Power State 504). The informationconcerning the current operating power state of the device includes anyone or more of whether increased power (e.g. to enable decreasedlatency) is a current objective, whether decreased power (e.g. at anexpense of increased latency) is a current objective, and otherinformation relating to, e.g., power and/or performance objectives. Thenthe device determines whether to transition to the specified power mode,e.g. to use the specified power mode as a new operating power mode (UseProvided? 505). If the device determines to use the specified power mode(Yes 505Y). then the device proceeds to set the specified power mode asthe (new specified) operating power mode (Set PHY Power Mode 507). Ifthe device determines not to use the specified power mode (No 505N),then the device proceeds to compute a new operating power mode(Determine New PHY Power Mode 506), based at least in part on thespecified power mode and the information concerning the currentoperating power state. In some scenarios, the new (computed) operatingpower mode is identical to a current operating power mode (e.g. there isno transition of operating power mode). Then the device proceeds to setthe specified power mode as the new (computed) operating power mode (SetPHY Power Mode 507). The flow then returns back (503) to continueoperating the interface in accordance with the new (either specified orcomputed) operating power mode (until receipt of another request tochange to a specific power mode).

FIG. 5 and the associated description are applicable to the interfaceoperating in the enhanced mode. Operation in the compatible mode issimilar, except that 504 is optionally omitted, 505 and 506 are omitted,and flow proceeds along 505Y unconditionally (e.g. flow proceedsdirectly from 503 or 504 to 507). As set forth, FIG. 5 and theassociated description are applicable to a context of an interface of adevice. In various embodiments and/or usage scenarios, FIG. 5 and theassociated description are applicable to an interface of a host (e.g.information concerning a current host operating power state is consultedinstead of information concerning a current device operating powerstate).

Following is a detailed description of an exemplary embodiment of devicepower control of an interface. A storage device (e.g. a SAS and/or aSATA compatible storage device) and/or a host include a PHY implementingthree power modes: active, partial, and slumber. The partial power modehas faster wake up time than the slumber power mode, e.g., a transitionfrom the partial power mode to the active power mode is 2 uS, and atransition from the slumber power mode to the active power mode is 500uS. In an operating scenario where a host is coupled to a storage devicevia a link, power mode transition request primitives exchanged on thelink request transitions to the partial and slumber power modes, such aspartial-power-mode-request and slumber-power-mode-request primitives(e.g. respectively primitives PMREQ_P and PMREQ_S for SAS and/or SATA).In various operating scenarios (e.g. while operating in the compatiblemode), the host and/or the storage device initiate sending theprimitives, and in response PHYs of the host and the storage devicetransition to the partial or slumber power mode, as indicated by theprimitive. PHY slumber mode is a lower-power mode than PHY partial powermode.

In some situations (e.g. while operating in the compatible mode), thePHY power mode is negotiated via one or more low level state machines,operating based on an amount of activity on the link, without overallsystem context. For example, if there is less than a first threshold ofactivity on the link, then a partial-power-mode-request primitive issent. Continuing with the example, if there is less than a secondthreshold of activity on the link, the second threshold being less thanthe first threshold, then a slumber-power-mode-request primitive issent. In some situations, however, a system including a host and astorage device is in an overall system context such that a relativelyhigh performance (e.g. relatively low latency) to wake up isadvantageous (at an expense of power), even though there is relativelyless activity on a link, or alternatively relatively high power savingsare advantageous (at an expense of latency), even though there isrelatively more activity on a link. Thus the state machines, in someinstances, negotiate a slumber power mode when a relatively low latencywould he advantageous, or alternatively negotiate a partial power modewhen relatively low power (e.g. relatively high power savings) would beadvantageous.

In some embodiments and/or usage scenarios (e.g. while operating in theenhanced mode), the PHYs of the host and/or the storage deviceselectively transition power modes based on other information inaddition to power mode transition request primitives. The otherinformation includes information concerning current operating powerstate, such as storage device power state information, usable todetermine, for example, if latency or power savings is to be optimized.For example, in response to a slumber-power-mode-request primitiveexchange, a storage device examines storage device power stateinformation, and determines that instead of transitioning to the slumberpower mode, latency is to be optimized, and the storage devicetransitions to the partial power mode. For another example, in responseto a partial-power-mode-request primitive exchange, a storage deviceexamines storage device power state information, and determines thatinstead of transitioning to the partial power mode, power saving is tobe optimized, and the storage device transitions to the slumber powermode.

Therefore rather than statically mapping an exchanged power modetransition request primitive directly into a PHY power mode transition(e.g. while operating in the compatible mode), storage device powerstate information is examined to determine the PHY power mode transition(e.g. while operating in the enhanced mode). Thus apartial-power-mode-request primitive is dynamically and/or selectivelymapped, based on storage device power state information, to either apartial power mode or a slumber power mode. Similarly, aslumber-power-mode-request primitive is dynamically and/or selectivelymapped, based on storage device power state information, to either apartial power mode or a slumber power mode. The dynamically and/orselectively mapping of the power mode transition request primitivesenables a system to be selectively optimized for performance or power.

FIG. 6 illustrates selected details of various embodiments of devicepower control with respect to device power management commands. Similarto FIGS. 2 and 4, the illustrated actions are performed variously by ahost (e.g. Host 102 of FIG. 1B) as illustrated by a dashed-box in thecenter portion of the figure (Host Actions 600H) and a device (e.g. aninstance of SSD 101 of FIG. 1B) as illustrated by the dashed-box in theright-hand portion of the figure (Device Actions 600D). The host iscoupled to and/or in communication with the device (e.g. as illustratedby Intermediate Interfaces 104 and optionally Switch/Fabric/IntermediateController 103 of FIG. 1B). In summary, a device is enabled to consult adevice power management command map to determine which of a plurality ofoperating power states to operate in accordance with in response toreception of a device power management command. A host runs software(optionally with user input) to send a power control command thatspecifies one or more modifications to the device power managementcommand map. Subsequently received device power management commands areinterpreted in accordance with the modifications. Thus mapping betweendevice power management commands and operating power states of thedevice is selectively and/or dynamically maintained.

More specifically, the actions begin (Start 601H). A host runs one ormore programs (Execute Software 602H), such as one or more power controlsoftware modules (e.g. all or any portions of Power Control Software 108of FIG. 1B). A user optionally initiates and/or optionally providesinput to the programs (User Input (optional) 602U), such as via entry ofone or more command strings and/or parameters. In response, the Softwaresends a power control command to the device (Issue Power Control Command(Modify Map) 603H). The power control command specifies one or moremodifications to a map (Device Power Management Command Map 604D) thatis used to translate device power management commands to respectivedevice operating power states. The device then accepts and processes thepower control command (Receive & Process Power Control Command 603D),including altering Device Power Management Command Map 604D as specifiedby the command.

Subsequently, the host sends a device power management command to thedevice (Issue Device Power Management Command 605H). In response, thedevice accepts and processes the power management command (Receive &Process Device Power Management Command 605D), including consultingDevice Power Management Command Map 604D to determine which of aplurality of operating power states to subsequently operate the devicein accordance with. Then the device proceeds to operate in accordancewith the determined operating power state. Actions are then complete(End 699D).

In various embodiments, the device power management command is issued inresponse to execution of one or more programs or portions thereof on thehost. For example, a device driver (e.g. Driver 107 of FIG. 1B)determines, such as due to inactivity and/or temperature overage, thatpower is to be reduced, and issues a device power management command toreduce power. For another example, an OS (e.g. OS 105 of FIG. 1B) orportion thereof determines, such as due to expected performancerequirements, that performance is to be increased (or at least allowedto increase). and issues a device power management command to increaseperformance (e.g. to exit a lower power and hence lower performancestate).

In various embodiments and/or usage scenarios, the map-modifying powercontrol command is optionally and/or selectively a queued command or isoptionally and/or selectively not a queued command. In variousembodiments, all or any portions of Device Power Management Command Map604D correspond to all or any portions of the information concerning thecurrent operating power state (e.g. as consulted with respect to 504 ofFIG. 5).

The following table describes a plurality of example mappings betweenparticular device power management commands (e.g. selected SATAcommands) and corresponding device operating power states (e.g. selectedSATA power states), such as indicated by information maintained inDevice Power Management Command Map 604D.

Device Power Management Device Operating Power State Command Default LowPower High Performance N/A Active Low Power High Performance IDLE IdleSleep High Performance STANDBY Standby Sleep High Performance SLEEPSleep Sleep High Performance

The column labeled “Default” represents mappings resulting from, e.g., a(map-modifying) power control command such as “set default device powermanagement command mappings”. After receipt and processing of the “setdefault device power management command mappings” power control command,Device Power Management Command Map 604D is modified so that devicepower management commands are mapped to similarly named device operatingpower states (IDLE

Idle, STANDBY

Standby, and SLEEP

Sleep). The column labeled “Low Power” represents mappings resultingfrom, e.g., a (map-modifying) power control command such as “set lowpower device power management command mappings”. After receipt andprocessing of the “set low power device power management commandmappings” power control command, Device Power Management Command Map604D is modified so that all of the device power management commands(IDLE, STANDBY, and SLEEP) are mapped to the lowest device operatingpower state (Sleep). The column labeled “High Performance” representsmappings resulting from, e.g., a (map-modifying) power control commandsuch as “set high performance device power management command mappings”.After receipt and processing of the “set high performance device powermanagement command mappings” power control command, Device PowerManagement Command Map 604D is modified so that all of the device powermanagement commands (IDLE, STANDBY, and SLEEP) are mapped to the highestdevice operating power state (High Performance).

Following is a detailed description of various exemplary embodiments ofdevice power control with respect to device power management commands.

In a first of the various exemplary embodiments, a storage device (e.g.a SATA compatible drive) is coupled to a host (e.g. a desktop computer).A user executes an application program on the desktop computer to alterhow the drive interprets device power management commands, e.g. bysending a “set high performance device power management commandmappings” power control command to the drive. Afterward the drive mapsall device power management commands to a high performance deviceoperating state, thus enabling high performance.

Subsequently the user uncouples the drive from the desktop computer andcouples it to a laptop computer. The user executes the application (or avariant thereof) on the laptop computer to again alter how the driveinterprets device power management commands, e.g. by sending a “set lowpower device power management command mappings” power control command tothe drive. Afterward the drive maps all device power management commandsto a sleep device operating state, thus enabling low power consumption.Then the user plugs the laptop computer into a wall outlet and executesthe application to send a “set high performance device power managementcommand mappings” power control command to the drive. In response thedrive maps all device power management commands to a high performancedevice operating state, thus enabling high performance. The user thenperforms one or more activities using the laptop computer (e.g. playinggames). When the user finishes the activities, the user executes theapplication to send a “set low power device power management commandmappings” power control command to the drive, enabling subsequent lowpower consumption operation of the drive.

In a second of the various exemplary embodiments, a storage device (e.g.a SATA compatible drive) is coupled to a host (e.g. a laptop computer).Software executing on the laptop computer (e.g. an application, adriver, and/or one or more portions of an OS) detects changes in how thelaptop is powered (e.g. outlet-powered or battery-powered). Upondetecting that the laptop computer is outlet-powered, the software sendsa “set high performance device power management command mappings”command to the drive, resulting in all device power management commandsbeing mapped to a high performance device operating state, thus enablinghigh performance operation of the drive. Upon detecting that the laptopcomputer is battery-powered, the software sends a “set low power devicepower management command mappings” command to the drive, resulting inall device power management commands being mapped to a sleep deviceoperating state, thus enabling low power consumption operation of thedrive. Therefore the behavior of the drive in response to the devicepower management commands is dynamically altered depending on anoperating power context (outlet-powered versus battery-powered).

In a third of the various exemplary embodiments, a storage device (e.g.a SATA compatible drive) is coupled to a host (e.g. a desktop or laptopcomputer). Software executing on the laptop computer (e.g. anapplication, a driver, and/or one or more portions of BIOS and/or an OS)dynamically configures the drive to operate within a specified powerbudget (e.g. envelope) based on system power and/or system performancegoals and/or objectives. For instance, when playing a game andoutlet-powered, the drive is configured for maximum performance. Whenrunning an application (e.g. not benefiting from high performance) andbattery-powered, the drive is configured for minimum power consumption.

In various embodiments, all or any portions of device actionsillustrated in any one or more of FIGS. 2-6 are performed wholly or inpart by any one or more of execution of one or more firmware modules, byoperation of one or more state machines, and/or by one or more hardwarelogic modules. For example, the operating power mode indicator ismaintained by execution of one or more portions of a firmware image(e.g. CPU 171 of FIG. 1A executing one or more portions of an instanceof FW 106 of FIG. 1B) such as by altering a value stored in volatile ornon-volatile memory (e.g. SPM 196 of FIG. 1B). For another example,Power Control 183 of FIG. 1A implements one or more portions of one ormore device actions illustrated in any one or more of FIGS. 2-6. For yetanother example, the information concerning the current operating powerstate of the device is maintained at least in part by execution of oneor more portions of a firmware image (e.g. CPU 171 of FIG. 1A executingone or more portions of an instance of FW 106 of FIG. 1B). For yetanother example, a device power management command map (e.g. DevicePower Management Command Map 604D of FIG. 6) is maintained at least inpart by execution of one or more portions of a firmware image (e.g. CPU171 of FIG. 1A executing one or more portions of an instance of FW 106of FIG. 1B) such as by altering a value stored in volatile ornon-volatile memory (e.g. a portion of NVM 199 of FIG. 1B).

Example Implementation Techniques

In some embodiments, various combinations of all or any portions ofoperations performed by a system, host, device, device controller,storage device, storage device controller, SSD, or SSD controllerenabled to operate in accordance with device power control, acomputing-host flash memory controller, and/or an SSD controller (suchas SSD Controller 100 of FIG. 1A), and portions of a processor,microprocessor, system-on-a-chip,application-specific-integrated-circuit, hardware accelerator, or othercircuitry providing all or portions of the aforementioned operations,are specified by a specification compatible with processing by acomputer system. The specification is in accordance with variousdescriptions, such as hardware description languages, circuitdescriptions, netlist descriptions, mask descriptions, or layoutdescriptions. Example descriptions include: Verilog, VHDL, SPICE, SPICEvariants such as PSpice, IBIS, LEF, DEF, GDS-II, OASIS, or otherdescriptions. In various embodiments, the processing includes anycombination of interpretation, compilation, simulation, and synthesis toproduce, to verify, or to specify logic and/or circuitry suitable forinclusion on one or more integrated circuits. Each integrated circuit,according to various embodiments, is designable and/or manufacturableaccording to a variety of techniques. The techniques include aprogrammable technique (such as a field or mask programmable gate arrayintegrated circuit), a semi-custom technique (such as a wholly orpartially cell-based integrated circuit), and a full-custom technique(such as an integrated circuit that is substantially specialized), anycombination thereof, or any other technique compatible with designand/or manufacturing of integrated circuits.

In some embodiments, various combinations of all or portions ofoperations as described by a computer readable medium having a set ofinstructions stored therein, are performed by execution and/orinterpretation of one or more program instructions, by interpretationand/or compiling of one or more source and/or script languagestatements, or by execution of binary instructions produced bycompiling, translating, and/or interpreting information expressed inprogramming and/or scripting language statements. The statements arecompatible with any standard programming or scripting language (such asC. C++, Fortran, Pascal, Ada, Java, VBscript, and Shell). One or more ofthe program instructions, the language statements. or the binaryinstructions, are optionally stored on one or more computer readablestorage medium elements. In various embodiments, some, all, or variousportions of the program instructions are realized as one or morefunctions, routines, sub-routines, in-line routines, procedures, macros,or portions thereof.

CONCLUSION

Certain choices have been made in the description merely for conveniencein preparing the text and drawings, and unless there is an indication tothe contrary, the choices should not be construed per se as conveyingadditional information regarding structure or operation of theembodiments described. Examples of the choices include: the particularorganization or assignment of the designations used for the figurenumbering and the particular organization or assignment of the elementidentifiers (the callouts or numerical designators, e.g.) used toidentify and reference the features and elements of the embodiments.

The words “comprises”, “comprising”, “includes”, and “including” arespecifically intended to be construed as abstractions describing logicalsets of open-ended (non-restrictive) scope and are not meant to conveyphysical containment unless explicitly followed by the word “within.”

Although the foregoing embodiments have been described in some detailfor purposes of clarity of description and understanding, the inventionis not limited to the details provided. There are many embodiments ofthe invention. The disclosed embodiments are exemplary and notrestrictive.

It will be understood that many variations in construction, arrangement,and use are possible consistent with the description, and are within thescope of the claims of the issued patent. For example, interconnect andfunction-unit bit-widths, clock speeds, and the type of technology usedare variable according to various embodiments in each component block.The names given to interconnect and logic are merely exemplary, andshould not be construed as limiting the concepts described. The orderand arrangement of flowchart and flow diagram process, action, andfunction elements are variable according to various embodiments. Also,unless specifically stated to the contrary, value ranges specified,maximum and minimum values used, or other particular specifications(such as flash memory technology types; and the number of entries orstages in registers and buffers), are merely those of the describedembodiments, are expected to track improvements and changes inimplementation technology, and should not be construed as limitations.

Functionally equivalent techniques known in the art are employableinstead of those described to implement various components, sub-systems,operations, functions, routines, sub-routines, in-line routines,procedures, macros, or portions thereof. It is also understood that manyfunctional aspects of embodiments are realizable selectively in eitherhardware (e.g., generally dedicated circuitry) or software (e.g., viasome manner of programmed controller or processor), as a function ofembodiment dependent design constraints and technology trends of fasterprocessing (facilitating migration of functions previously in hardwareinto software) and higher integration density (facilitating migration offunctions previously in software into hardware). Specific variations invarious embodiments include, but are not limited to: differences inpartitioning; different form factors and configurations; use ofdifferent operating systems and other system software; use of differentinterface standards, network protocols, or communication links; andother variations to be expected when implementing the concepts describedherein in accordance with the unique engineering and businessconstraints of a particular application.

The embodiments have been described with detail and environmentalcontext well beyond that required for a minimal implementation of manyaspects of the embodiments described. Those of ordinary skill in the artwill recognize that some embodiments omit disclosed components orfeatures without altering the basic cooperation among the remainingelements. It is thus understood that much of the details disclosed arenot required to implement various aspects of the embodiments described.To the extent that the remaining elements are distinguishable from theprior art, components and features that are omitted are not limiting onthe concepts described herein.

All such variations in design are insubstantial changes over theteachings conveyed by the described embodiments. It is also understoodthat the embodiments described herein have broad applicability to othercomputing and networking applications, and are not limited to theparticular application or industry of the described embodiments. Theinvention is thus to be construed as including all possiblemodifications and variations encompassed within the scope of the claimsof the issued patent.

What is claimed is:
 1. A method comprising: receiving, at a storage controller operably connected to a storage device, a first command and then a second command, the second command comprising power control information; and processing, by the storage controller, the second command in response to the receiving while the first command is outstanding.
 2. The method of claim 1, further comprising operating the storage device in accordance with at least a portion of the power control information across a reset and/or a power cycle of the storage device.
 3. The method of claim 1, further comprising processing the first command in accordance with the power control information.
 4. The method of claim 1, wherein the storage device comprises one or more flash memory devices, and the processing comprises altering how many of the flash memory devices are maximally enabled to be concurrently active.
 5. The method of claim 1, further comprising the storage controller passing along at least a portion of the power control information to at least one other storage device.
 6. The method of claim 5, wherein the first and second commands are received from a host operably connected to the storage controller, the method further comprising: receiving, at the storage controller, power usage information from the at least one other storage device; and passing along, by the storage controller, at least a portion of the power usage information to the host.
 7. The method of claim 1, wherein the processing comprises dynamically modifying mapping information in the storage controller based on the power control information, the mapping information comprising mappings between device power management commands and device operating power states, the method further comprising: receiving, at the storage controller, a device power management command to transition the operation of the storage device to a specified operating power state; based on the specified operating power state in the device power management command and the mapping information, determining a new operating power state for the storage device; and operating the storage device in accordance with the new operating power state, wherein the new operating power state is different than the specified operating power state.
 8. The method of claim 7, wherein the device power management commands comprising the mapping information comprise one or more of an IDLE command, a STANDBY command, and a SLEEP command.
 9. A non-transitory computer readable medium containing processor-executable instructions that, when executed by a processing element of a storage controller operably connected to a storage device, cause the storage controller to: receive a first command and then a second command from a host, the second command comprising power control information; and process the second command in response to the receiving while the first command is outstanding.
 10. The non-transitory computer readable medium of claim 9, containing further processor-executable instructions that cause the storage controller to operate the storage device in accordance with at least a portion of the power control information across a reset and/or a power cycle of the storage device.
 11. The non-transitory computer readable medium of claim 9, containing further processor-executable instructions that cause the storage controller to process the first command in accordance with the power control information.
 12. The non-transitory computer readable medium of claim 9, wherein the storage device comprises one or more flash memory devices, and the processing comprises altering how many of the flash memory devices are maximally enabled to be concurrently active.
 13. The non-transitory computer readable medium of claim 9, containing further processor-executable instructions that cause the storage controller to pass along at least a portion of the power control information to at least one other storage device.
 14. The non-transitory computer readable medium of claim 13, containing further processor-executable instructions that cause the storage controller to receive power usage information from the at least one other storage device and pass along at least a portion of the power usage information to the host.
 15. The non-transitory computer readable medium of claim 9, wherein the processing comprises dynamically modifying mapping information in the storage controller based on the power control information, the mapping information comprising mappings between device power management commands and device operating power states, and wherein the non-transitory computer readable medium contains further processor-executable instructions that cause the storage controller to: receive a device power management command to transition the operation of the storage device to a specified operating power state; based on the specified operating power state in the device power management command and the mapping information, determine a new operating power state for the storage device; and operate the storage device in accordance with the new operating power state, wherein the new operating power state is different than the specified operating power state.
 16. A storage device comprising: a non-volatile memory comprising one or more flash memory devices; and a controller operably connected to the non-volatile memory and configured to: receive a first command and then a second command, the second command comprising power control information, and process the second command in response to the receiving while the first command is outstanding.
 17. The storage device of claim 16, wherein the controller is further configured to operate the storage device in accordance with at least a portion of the power control information across a reset and/or a power cycle of the storage device.
 18. The storage device of claim 16, wherein the processing comprises altering how many of the one or more flash memory devices are maximally enabled to be concurrently active.
 19. The storage device of claim 16, wherein the processing comprises dynamically modifying mapping information in the controller based on the power control information, the mapping information comprising mappings between device power management commands and device operating power states, the controller further configured to: receive a device power management command to transition the operation of the storage device to a specified operating power state; based on the specified operating power state in the device power management command and the mapping information, determine a new operating power state for the storage device; and operate the storage device in accordance with the new operating power state, wherein the new operating power state is different than the specified operating power state.
 20. The storage device of claim 19, wherein the device power management commands comprising the mapping information comprise one or more of an IDLE command, a STANDBY command, and a SLEEP command. 